Abstract: A motor control circuit includes a first switch module, a three-phase inverter, and a control module. A power supply module, the first switch module, the three-phase inverter, and a three-phase alternating current motor form a current loop; midpoints of three phase legs of the three-phase inverter are respectively connected to three phase coils of the three-phase alternating current motor; the three-phase alternating current motor is configured to input or output a current by using a wire N extending from a connection point of the three phase coils; the control module is connected to the three-phase inverter, first switch module, three-phase alternating current motor, and power supply module; the control module is configured to control the three-phase inverter to enable the motor control circuit to receive a voltage of the power supply module and output a direct current, and to boost a voltage of the power supply module.

Abstract: An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

Abstract: Provided are a mode conversion method and a mode conversion apparatus for a nonvolatile memory. The method includes: receiving a first user command that is sent by an upper computer and belongs to a user mode, where the first user command includes an invoking path disabling instruction; sending an enable signal according to the invoking path disabling instruction; and disabling the module path for controlling the high-bit I/O ports [15:8] in the X16 nonvolatile memory according to the enable signal. After the module path for controlling the high-bit I/O ports [15:8] in the nonvolatile memory is disabled, data transmission and reception of the nonvolatile memory are implemented through the low-bit I/O ports [7:0], and the X16 nonvolatile memory is converted into an X8 mode.

Abstract: An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.

Abstract: An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.

Abstract: An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.

Abstract: Disclosed are an enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve performance of the chip.