Abstract: A temperature-regulating unit includes a base, a resonant tank, and a controller. The base is configured to support a pan. The resonant tank includes a coil and a capacitor. The resonant tank has a resonant frequency that is affected by a material of the pan and a temperature of the pan. The controller is configured to receive a temperature setting, monitor the resonant frequency, determine the material of the pan based on the resonant frequency, determine the temperature of the pan based on the resonant frequency, and adaptively control a thermal element based on the temperature of the pan, the material of the pan, and the temperature setting.

Abstract: A temperature-regulating unit includes a base, a thermal element, a contactless sensing assembly, and a controller. The base is configured to support at least one of a pan or a food product. The thermal element is positioned to thermally regulate the at least one of the pan or the food product. The contactless sensing assembly is positioned to acquire sensor data regarding the at least one of the pan or the food product. The controller is configured to receive the sensor data from the contactless sensing assembly and adaptively control the thermal element based on the sensor data.

Abstract: A temperature-regulating unit includes a base, a thermal element, a contactless sensing assembly, and a controller. The base is configured to support at least one of a pan or a food product. The thermal element is positioned to thermally regulate the at least one of the pan or the food product. The contactless sensing assembly is positioned to acquire sensor data regarding the at least one of the pan or the food product. The controller is configured to receive the sensor data from the contactless sensing assembly and adaptively control the thermal element based on the sensor data.

Abstract: Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.

Abstract: Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.