Patents by Inventor Ronghui Gu

Ronghui Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240419808
    Abstract: Mechanisms for verifying software are provided, the mechanisms including: identifying a plurality of layers of code of the software including a lowest layer, a middle layer, and a highest layer; generating a low-level specification and an identical refinement proof for each of the plurality of layers using a hardware processor; generating a high-level specification and a lifting refinement proof for each of the plurality of layers; and verifying the software based on the low-level specifications, the identical refinement proofs, the high-level specifications, and the lifting refinement proofs. In some embodiments, one of the low-level specifications is generated using Fixedpoint construction. In some embodiments, one of the high-level specifications is generated by applying a set of transformation rules to one of the low-level specifications.
    Type: Application
    Filed: June 17, 2024
    Publication date: December 19, 2024
    Inventors: Jason Nieh, Wei Qiang, Xuheng Li, Xupeng Li, Ronghui Gu
  • Patent number: 12079102
    Abstract: Mechanisms for proving the correctness of software on relaxed memory hardware are provided, the mechanisms comprising: receiving a specification, a hardware model, and an implementation for the software to be executed on the relaxed memory hardware; evaluating the software using a sequentially consistent hardware model; evaluating the software using a relaxed memory hardware model and at least one of the following conditions: a data-race-free (DRF)-kernel condition; a no-barrier-misuse condition; a memory-isolation condition; a transactional-page-table condition; a write-once-kernel-mapping condition; and a weak-memory-isolation condition; and outputting an indication of whether the software is correct based on the evaluating the software using the sequentially consistent hardware model and the evaluating the software using the relaxed memory hardware model.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 3, 2024
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Ronghui Gu, Jason Nieh, Runzhou Tao
  • Publication number: 20240012728
    Abstract: Mechanisms for verifying software on a multi-CPU machine are provided, the mechanisms including: using a hardware processor: reordering, in a shared log, a first local CPU event from a local CPU operating on a shared object to be before at least one first prior oracle query corresponding to a prior event from another CPU based on whether the first local CPU event can be reordered with respect to the prior event without changing the multi-CPU machine's behavior with respect to the shared object; merging first consecutive oracle queries including the at least one first prior oracle query in the shared log; and verifying the software based on the merged first consecutive oracle queries.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 11, 2024
    Inventors: Jason Nieh, Ronghui Gu, Xuheng Li, Xupeng Li
  • Patent number: 11816018
    Abstract: Systems and methods for formal verification of programs. The systems and methods provide a new game-theoretical, strategy-based compositional semantic model for concurrency, a set of formal linking theorems for composing multithreaded and multicore concurrent layers, and a compiler that supports certified thread-safe compilation and linking. Verification of an overlay interface can include determining an intermediate strategy for a primitive operation running on an underlay interface and refining that intermediate strategy to a strategy running on the overlay interface by applying a vertical and a horizontal composition rule. The refined strategy can then be composed with compatible strategies running on the overlay interface according to a parallel composition rule. Strategies may be compatible when rely conditions imposed by each strategy satisfy guarantees provided by the other strategies. The system and method of formal verification can be applied to formal verification of smart contracts.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: November 14, 2023
    Assignee: Yale University
    Inventors: Zhong Shao, Ronghui Gu, Vilhelm Sjoberg, Jieung Kim, Jeremie Koenig
  • Publication number: 20220365862
    Abstract: Systems and methods for formal verification of programs. The systems and methods provide a new game-theoretical, strategy-based compositional semantic model for concurrency, a set of formal linking theorems for composing multithreaded and multicore concurrent layers, and a compiler that supports certified thread-safe compilation and linking. Verification of an overlay interface can include determining an intermediate strategy for a primitive operation running on an underlay interface and refining that intermediate strategy to a strategy running on the overlay interface by applying a vertical and a horizontal composition rule. The refined strategy can then be composed with compatible strategies running on the overlay interface according to a parallel composition rule. Strategies may be compatible when rely conditions imposed by each strategy satisfy guarantees provided by the other strategies. The system and method of formal verification can be applied to formal verification of smart contracts.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 17, 2022
    Applicant: Yale University
    Inventors: Zhong Shao, Ronghui Gu, Vilhelm Sjoberg, Jieung Kim, Jeremie Koenig
  • Patent number: 11409630
    Abstract: Systems and methods for formal verification of programs. The systems and methods provide a new game-theoretical, strategy-based compositional semantic model for concurrency, a set of formal linking theorems for composing multithreaded and multicore concurrent layers, and a compiler that supports certified thread-safe compilation and linking. Verification of an overlay interface can include determining an intermediate strategy for a primitive operation running on an underlay interface and refining that intermediate strategy to a strategy running on the overlay interface by applying a vertical and a horizontal composition rule. The refined strategy can then be composed with compatible strategies running on the overlay interface according to a parallel composition rule. Strategies may be compatible when rely conditions imposed by each strategy satisfy guarantees provided by the other strategies. The system and method of formal verification can be applied to formal verification of smart contracts.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 9, 2022
    Assignee: Yale University
    Inventors: Zhong Shao, Ronghui Gu, Vilhelm Sjoberg, Jieung Kim, Jeremie Koenig
  • Publication number: 20220019514
    Abstract: Mechanisms for proving the correctness of software on relaxed memory hardware are provided, the mechanisms comprising: receiving a specification, a hardware model, and an implementation for the software to be executed on the relaxed memory hardware; evaluating the software using a sequentially consistent hardware model; evaluating the software using a relaxed memory hardware model and at least one of the following conditions: a data-race-free (DRF)-kernel condition; a no-barrier-misuse condition; a memory-isolation condition; a transactional-page-table condition; a write-once-kernel-mapping condition; and a weak-memory-isolation condition; and outputting an indication of whether the software is correct based on the evaluating the software using the sequentially consistent hardware model and the evaluating the software using the relaxed memory hardware model.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 20, 2022
    Inventors: Ronghui Gu, Jason Nieh, Runzhou Tao
  • Publication number: 20200409740
    Abstract: Systems comprising: a memory; and a hardware processor and configured to: execute a hypervisor having a first portion and a second portion, wherein the first portion of the hypervisor executes at a first exception level that allows the first portion to access data of a virtual machine in the hardware processor and the memory, and wherein the second portion of the hypervisor executes at a second exception level that prevents the second portion from accessing the data of the virtual machine in the hardware processor and the memory. Methods comprising: executing a first portion of a hypervisor at a first exception level that allows the first portion to access data of a virtual machine in a hardware processor and memory; and executing a second portion of a hypervisor at a second exception level that prevents the second portion from accessing the data in the hardware processor and the memory.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 31, 2020
    Inventors: Shih-Wei Li, Xupeng Li, Ronghui Gu, Jason Nieh
  • Publication number: 20200387440
    Abstract: Systems and methods for formal verification of programs. The systems and methods provide a new game-theoretical, strategy-based compositional semantic model for concurrency, a set of formal linking theorems for composing multithreaded and multicore concurrent layers, and a compiler that supports certified thread-safe compilation and linking. Verification of an overlay interface can include determining an intermediate strategy for a primitive operation running on an underlay interface and refining that intermediate strategy to a strategy running on the overlay interface by applying a vertical and a horizontal composition rule. The refined strategy can then be composed with compatible strategies running on the overlay interface according to a parallel composition rule. Strategies may be compatible when rely conditions imposed by each strategy satisfy guarantees provided by the other strategies. The system and method of formal verification can be applied to formal verification of smart contracts.
    Type: Application
    Filed: November 28, 2018
    Publication date: December 10, 2020
    Applicant: Yale University
    Inventors: Zhong Shao, Ronghui Gu, Vilhelm Sjoberg, Jieung Kim, Jeremie Koenig