Abstract: A MOG circuit and a display panel are provided. The MOG circuit controls the current-stage MOG circuit through the first node signal to block the input of the MUX signal. At the same time, the MOG circuit controls the current-stage MUX circuit through the second node signal such that the voltage level of the scan signal is pulled down to the voltage level of the first low voltage level signal. In this way, all the scan signals could satisfy the turn-off stage while the MUX circuit has a lower loading capability.

Abstract: A display panel is provided. In the display panel, a plurality of first output terminals are arranged along an extending direction of a first side of a drive chip, a plurality of second output terminals are disposed on a side of the first output terminals away from a display area, and the plurality of second output terminals are disposed in an area between the plurality of first output terminals and an input terminal. Each second fan-out trace is electrically connected with a corresponding second output terminal through a second side of an adjacent drive chip, so that the drive chip can be moved upward as a whole and a lower frame can be reduced. A display device is also provided.

Abstract: A MOG circuit and a display panel are provided. The MOG circuit controls the current-stage MOG circuit through the first node signal to block the input of the MUX signal. At the same time, the MOG circuit controls the current-stage MUX circuit through the second node signal such that the voltage level of the scan signal is pulled down to the voltage level of the first low voltage level signal. In this way, all the scan signals could satisfy the turn-off stage while the MUX circuit has a lower loading capability.

Abstract: A display panel includes an array substrate, a plurality of cascading GOA units, a plurality of DEMUX switching units, and a DEMUX control signal generating circuit. One DEMUX switching unit includes a scanning signal input port, at least two control signal input ports, and at least two scanning signal output ports. One GOA unit is connected to the scanning signal input port, the DEMUX control signal generating circuit is connected to the at least two control signal input ports, and the scanning signal output ports are connected to corresponding gate lines.

Abstract: A demultiplexer gate driver circuit and a display panel are provided. The demultiplexer gate driver circuit aims at the problem that the output amplitude of the m sub-gate drive signals divided from the gate drive signal by the demultiplexer module is low, which results in a poorer All Gate On function, when the GOA circuit of the demultiplexer module is used to achieve the All Gate On function. The full-on control module is improved by connecting the full-on control module to the m sub-gate drive signals divided from the gate drive signal. The m sub-gate drive signals are directly controlled by the full-on control module to output the high potential at the same time, and there is only one threshold voltage consumption from the full-on control signal to the sub-gate drive signals. The effect of the All Gate On function is effectively improved.

Abstract: A display panel includes an array substrate, a plurality of cascading GOA units, a plurality of DEMUX switching units, and a DEMUX control signal generating circuit. One DEMUX switching unit includes a scanning signal input port, at least two control signal input ports, and at least two scanning signal output ports. One GOA unit is connected to the scanning signal input port, the DEMUX control signal generating circuit is connected to the at least two control signal input ports, and the scanning signal output ports are connected to corresponding gate lines.

Abstract: A demultiplexer gate driver circuit and a display panel are provided. The demultiplexer gate driver circuit aims at the problem that the output amplitude of the m sub-gate drive signals divided from the gate drive signal by the demultiplexer module is low, which results in a poorer All Gate On function, when the GOA circuit of the demultiplexer module is used to achieve the All Gate On function. The full-on control module is improved by connecting the full-on control module to the m sub-gate drive signals divided from the gate drive signal. The m sub-gate drive signals are directly controlled by the full-on control module to output the high potential at the same time, and there is only one threshold voltage consumption from the full-on control signal to the sub-gate drive signals. The effect of the All Gate On function is effectively improved.

Abstract: A test circuit for preventing an electrostatic discharge (ESD) device from electricity leakage and a display panel having the same are provided. The test circuit includes a switch module between the ESD device and the display panel to control an electrical connection between the ESD device and the display panel, and prevent the display panel from electricity leakage, so as to reduce power consumption.

Abstract: The present invention teaches a Gate Driver on Array (GOA) circuit for a display panel. The GOA circuit includes a first dummy GOA unit and/or a second dummy GOA unit not connecting scan lines of the display panel's active area, and normal GOA units connecting scan lines of the active area. The normal GOA units are cascaded into a chain. The first dummy GOA unit is cascaded to a first normal GOA unit of the chain and/or the second dummy GOA unit is cascaded to a last normal GOA unit of the chain. A start signal of the display panel's vertical scanning as a cascaded signal is input into the first dummy GOA unit and/or the second dummy GOA unit. The GOA circuit excludes the line of afterimage from the active area, thereby allowing the fast black frame insertion after abnormal shutdown.

Abstract: The present invention teaches a Gate Driver on Array (GOA) circuit for a display panel. The GOA circuit includes a first dummy GOA unit and/or a second dummy GOA unit not connecting scan lines of the display panel's active area, and normal GOA units connecting scan lines of the active area. The normal GOA units are cascaded into a chain. The first dummy GOA unit is cascaded to a first normal GOA unit of the chain and/or the second dummy GOA unit is cascaded to a last normal GOA unit of the chain. A start signal of the display panel's vertical scanning as a cascaded signal is input into the first dummy GOA unit and/or the second dummy GOA unit. The GOA circuit excludes the line of afterimage from the active area, thereby allowing the fast black frame insertion after abnormal shutdown.

Abstract: A gate driver on array (GOA) circuit display panel is disclosed and achieves control to a voltage of a leakage path by a gate electrode signal of a seventh thin film transistor in a voltage regulation module. The display panel eliminates a stop leakage path of a touch panel by changing a signal.

Abstract: A GOA circuit comprises m cascaded GOA units, wherein a GOA unit comprises forward-reverse scan control module, first gate signal output module and second gate signal output module. The forward-reverse scan control module controls the GOA circuit to perform forward scanning or reverse scanning. The first gate signal output module comprises seventh TFT, ninth TFT and sixteenth TFT; a second terminal of the sixteenth TFT receives a high potential signal, and a first and a third terminal of the sixteenth TFT are connected to the first and second terminals of the seventh TFT, respectively. The second gate signal output module comprises twelfth TFT, thirteenth TFT and fifteenth TFT; a second terminal of the fifteenth TFT receives the high potential signal, and a first and a third terminal of the fifteenth TFT are connected to the first and second terminals of the twelfth TFT, respectively.

Abstract: Embodiments of the present application provides an array substrate, testing method and display apparatus. The array substrate comprises a testing circuit, pixel units and data lines connecting to the pixel units. The data lines are used for providing data signals to the pixel units and are arranged to extend along a first direction. The testing circuit comprises a switching unit and testing units. The switching unit comprises a first number of first switching elements parallelly arranged along the first direction, and the testing units are parallelly arranged along a second direction perpendicular to the first direction. By using the present application, performance of substrate testing can be ensured while achieving narrow boarder, and user experiences could be easily improved.

Abstract: A test circuit for preventing an electrostatic discharge (ESD) device from electricity leakage and a display panel having the same are provided. The test circuit includes a switch module between the ESD device and the display panel to control an electrical connection between the ESD device and the display panel, and prevent the display panel from electricity leakage, so as to reduce power consumption.

Abstract: A GOA circuit comprises m cascaded GOA units, wherein a GOA unit comprises forward-reverse scan control module, first gate signal output module and second gate signal output module. The forward-reverse scan control module controls the GOA circuit to perform forward scanning or reverse scanning. The first gate signal output module comprises seventh TFT, ninth TFT and sixteenth TFT; a second terminal of the sixteenth TFT receives a high potential signal, and a first and a third terminal of the sixteenth TFT are connected to the first and second terminals of the seventh TFT, respectively. The second gate signal output module comprises twelfth TFT, thirteenth TFT and fifteenth TFT; a second terminal of the fifteenth TFT receives the high potential signal, and a first and a third terminal of the fifteenth TFT are connected to the first and second terminals of the twelfth TFT, respectively.

Abstract: The present application provides a single-type GOA circuit comprising a controllable signal setting unit for providing a controllable signal. The controllable signal is held at a potential of a constant low-level voltage source when the circuit is operated in normal status, and at a potential of a constant high-level voltage source when the circuit is in a transmission suspended period. The potential of the signals in the current leakage path in the transmission suspended period is changed in the application so that voltage controlling and leakage path eliminating could be achieved and stability of the circuit is increased.

Abstract: The embodiments of the present disclosure disclose an array substrate, a display panel and a display device. The array substrate include a substrate body, a plurality of data signal lines, a plurality of touch signal lines, a plurality of first fan-out lines and a plurality of second fan-out lines. The substrate body includes an active area and a non-active area, and the non-active area includes a fan-out area adjacent to the active area. The plurality of first fan-out lines are connected to the plurality of data signal lines in a one-to-one correspondence manner. The plurality of second fan-out lines are connected to the plurality of touch signal lines in a one-to-one correspondence manner. The plurality of first fan-out lines and the plurality of second fan-out lines are made from the same material and located on the same layer.

Abstract: A gate driving circuit provided in the disclosure comprises a pull-up control module configured to generate a first control signal when power is turned off, a pull-up output module configured to output a high potential under control of the first control signal, a pull-down control module configured to generate a second control signal when power is turned off, and a pull-down output module configured to output a low potential under control of the second control signal. Wherein, the output terminals of the pull-up output module and the pull-down output module are connected to the output terminal of a Nth-stage gate driving unit, and, when power is turned off, the pull-up output module and the pull-down output module together make the output terminal of the Nth-stage gate driving unit output the high potential. The image remained on the liquid crystal screen when power is turned off suddenly is cleaned quickly thereby.

Abstract: The disclosure provides a GOA driving circuit comprising a plurality of GOA driving unit stages. When power is turned off, the pull-up control module controls the pull-up output module to stop outputting the clock signal, the pull-down control module controls the pull-down output module to stop outputting the low potential signal, the first global control module outputs the high potential signal, the reset module stops outputting the reset signal, and the second global control module stops outputting the low potential signal. Generation of the residual image on the liquid crystal screen is prevented when power is turned off.

Abstract: The disclosure provides a GOA driving circuit comprising a plurality of GOA driving unit stages. When power is turned off, the pull-up control module controls the pull-up output module to stop outputting the clock signal, the pull-down control module controls the pull-down output module to stop outputting the low potential signal, the first global control module outputs the high potential signal, the reset module stops outputting the reset signal, and the second global control module stops outputting the low potential signal. Generation of the residual image on the liquid crystal screen is prevented when power is turned off.