Patents by Inventor Rongming Chu

Rongming Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200273958
    Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Applicant: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Publication number: 20200227542
    Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Applicant: HRL Laboratories, LLC
    Inventors: Rongming CHU, Yu CAO
  • Publication number: 20200203931
    Abstract: A laser or light emitter for operation at a cryogenic temperature includes a single quantum well layer, an n-type barrier layer directly on a first surface of the single quantum well layer, and a p-type barrier layer directly on a second surface of the single quantum well layer opposite the first surface of the single quantum well layer. The single quantum well layer is between the p-type barrier layer and the n-type barrier layer and the compositions of the n-type barrier layer and the p-type barrier layer are graded.
    Type: Application
    Filed: October 21, 2019
    Publication date: June 25, 2020
    Inventors: Daniel Yap, Rongming CHU, Andrew PAN
  • Patent number: 10692984
    Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 23, 2020
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10659032
    Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: May 19, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Brian Hughes, Rongming Chu
  • Patent number: 10651306
    Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 12, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao
  • Patent number: 10535518
    Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 14, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
  • Patent number: 10387792
    Abstract: A device for storing and/or transferring quantum data. The device has a plurality of elongate semiconductor structures arranged in side by said with each elongate semiconductor structure having a quantum well layer of one semiconductor material disposed between upper and lower layers of a different semiconductor material which share the same or essentially the same crystalline structure as that of the quantum well layer. Neighboring ones of the elongate semiconductor structures share a region forming a constriction between the neighboring ones of the elongate semiconductor structures.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 20, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Thaddeus D. Ladd, Andrey A. Kiselev, Danny M. Kim, Rongming Chu
  • Publication number: 20190189762
    Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Applicant: HRL Laboratories, LLC
    Inventor: Rongming CHU
  • Publication number: 20190165154
    Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Inventors: Zijian "Ray" LI, Rongming CHU
  • Publication number: 20190165776
    Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 30, 2019
    Applicant: HRL Laboratories, LLC
    Inventors: Brian HUGHES, Rongming CHU
  • Patent number: 10283358
    Abstract: Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p?GaN material on a n?GaN vertical surface extending vertically from an n?GaN horizontal surface on an n?GaN drift layer to form a first PN junction, wherein the n?GaN horizontal surface extends horizontally from the n?GaN vertical surface and the n?GaN horizontal surface has a layer of dielectric material formed on the n?GaN horizontal surface that extends from the p?GaN surface.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 7, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao
  • Patent number: 10276712
    Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: April 30, 2019
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10263104
    Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 16, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Zijian “Ray” Li, Rongming Chu
  • Publication number: 20190067464
    Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Applicant: HRL Laboratories, LLC
    Inventors: Rongming CHU, Yu Cao
  • Patent number: 10199217
    Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: February 5, 2019
    Assignee: Transphorm Inc.
    Inventors: Rongming Chu, Umesh Mishra, Rakesh K. Lal
  • Patent number: 10181400
    Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 15, 2019
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10153761
    Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: December 11, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Brian Hughes, Rongming Chu
  • Publication number: 20180337042
    Abstract: Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p?GaN material on a n?GaN vertical surface extending vertically from an n?GaN horizontal surface on an n?GaN drift layer to form a first PN junction, wherein the n?GaN horizontal surface extends horizontally from the n?GaN vertical surface and the n?GaN horizontal surface has a layer of dielectric material formed on the n?GaN horizontal surface that extends from the p?GaN surface.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 22, 2018
    Applicant: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao
  • Patent number: 10134851
    Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 20, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao, Zijian “Ray” Li, Adam J. Williams