Patents by Inventor Rongming Chu
Rongming Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030356Abstract: Embodiments relate a super-heterojunction structure. A n-type modulation doping with barrier layer induces a two-dimensional electron gas (2DEG) channel and allows for vertically stacked channels without risk of reaching critical thickness limited by the strain in epitaxy. The n-type modulation doped layer is adjacent the at least one p-type layer to generate a charge balanced super-heterojunction region. A p-type ohmic contact ensures that the processes of depleting and accumulating of electrons and holes in the structure are fast enough for practical switching operation.Type: ApplicationFiled: October 5, 2021Publication date: January 25, 2024Inventors: Sang-Woo Han, Jianan Song, Rongming Chu, Mansura Sadek
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Patent number: 11437485Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: GrantFiled: December 22, 2020Date of Patent: September 6, 2022Assignee: HRL LABORATORIES, LLCInventors: Yu Cao, Rongming Chu, Zijian Ray Li
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Patent number: 11361965Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.Type: GrantFiled: October 19, 2020Date of Patent: June 14, 2022Assignee: HRL Laboratories, LLCInventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
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Patent number: 11183573Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.Type: GrantFiled: May 8, 2020Date of Patent: November 23, 2021Assignee: HRL Laboratories, LLCInventor: Rongming Chu
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Publication number: 20210151578Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: ApplicationFiled: December 22, 2020Publication date: May 20, 2021Applicant: HRL Laboratories, LLCInventors: Yu CAO, Rongming CHU, Zijian "Ray" LI
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Patent number: 10943998Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.Type: GrantFiled: March 25, 2020Date of Patent: March 9, 2021Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao
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Patent number: 10937650Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.Type: GrantFiled: November 6, 2019Date of Patent: March 2, 2021Assignee: HRL Laboratories, LLCInventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
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Patent number: 10916647Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: GrantFiled: January 31, 2019Date of Patent: February 9, 2021Assignee: HRL Laboratories, LLCInventors: Zijian “Ray” Li, Rongming Chu
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Patent number: 10910793Abstract: A laser or light emitter for operation at a cryogenic temperature includes a single quantum well layer, an n-type barrier layer directly on a first surface of the single quantum well layer, and a p-type barrier layer directly on a second surface of the single quantum well layer opposite the first surface of the single quantum well layer. The single quantum well layer is between the p-type barrier layer and the n-type barrier layer and the compositions of the n-type barrier layer and the p-type barrier layer are graded.Type: GrantFiled: October 21, 2019Date of Patent: February 2, 2021Assignee: HRL Laboratories, LLCInventors: Daniel Yap, Rongming Chu, Andrew Pan
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Patent number: 10903333Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: GrantFiled: July 28, 2017Date of Patent: January 26, 2021Assignee: HRL Laboratories, LLCInventors: Yu Cao, Rongming Chu, Zijian Ray Li
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Publication number: 20200273958Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Applicant: HRL Laboratories, LLCInventor: Rongming Chu
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Publication number: 20200227542Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.Type: ApplicationFiled: March 25, 2020Publication date: July 16, 2020Applicant: HRL Laboratories, LLCInventors: Rongming CHU, Yu CAO
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Publication number: 20200203931Abstract: A laser or light emitter for operation at a cryogenic temperature includes a single quantum well layer, an n-type barrier layer directly on a first surface of the single quantum well layer, and a p-type barrier layer directly on a second surface of the single quantum well layer opposite the first surface of the single quantum well layer. The single quantum well layer is between the p-type barrier layer and the n-type barrier layer and the compositions of the n-type barrier layer and the p-type barrier layer are graded.Type: ApplicationFiled: October 21, 2019Publication date: June 25, 2020Inventors: Daniel Yap, Rongming CHU, Andrew PAN
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Patent number: 10692984Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.Type: GrantFiled: February 25, 2019Date of Patent: June 23, 2020Assignee: HRL Laboratories, LLCInventor: Rongming Chu
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Patent number: 10659032Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.Type: GrantFiled: November 5, 2018Date of Patent: May 19, 2020Assignee: HRL Laboratories, LLCInventors: Brian Hughes, Rongming Chu
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Patent number: 10651306Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.Type: GrantFiled: August 25, 2017Date of Patent: May 12, 2020Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao
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Patent number: 10535518Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.Type: GrantFiled: March 26, 2018Date of Patent: January 14, 2020Assignee: HRL Laboratories, LLCInventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
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Patent number: 10387792Abstract: A device for storing and/or transferring quantum data. The device has a plurality of elongate semiconductor structures arranged in side by said with each elongate semiconductor structure having a quantum well layer of one semiconductor material disposed between upper and lower layers of a different semiconductor material which share the same or essentially the same crystalline structure as that of the quantum well layer. Neighboring ones of the elongate semiconductor structures share a region forming a constriction between the neighboring ones of the elongate semiconductor structures.Type: GrantFiled: June 29, 2017Date of Patent: August 20, 2019Assignee: HRL Laboratories, LLCInventors: Thaddeus D. Ladd, Andrey A. Kiselev, Danny M. Kim, Rongming Chu
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Publication number: 20190189762Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Applicant: HRL Laboratories, LLCInventor: Rongming CHU
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Publication number: 20190165776Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.Type: ApplicationFiled: November 5, 2018Publication date: May 30, 2019Applicant: HRL Laboratories, LLCInventors: Brian HUGHES, Rongming CHU