Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material; a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials; a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure; and a capping material over the gate metal and the plurality of additional workfunction materials.

Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.

Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material; a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials; a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure; and a capping material over the gate metal and the plurality of additional workfunction materials.

Abstract: An apparatus for in situ fabrication of multilayer heterostructures is provided comprising a first vacuum chamber adapted for atomic layer deposition and comprising a first stage docking assembly configured to dock a detachable stage configured to support a substrate; a second vacuum chamber adapted for ultra-high vacuum physical or chemical vapor deposition and comprising a second stage docking assembly configured to dock the detachable stage; a load lock vacuum chamber between the first and second vacuum chambers and comprising a third stage docking assembly configured to dock the detachable stage, the load lock vacuum chamber coupled to the first vacuum chamber via a first shared valve and coupled to the second vacuum chamber via a second shared valve; and a substrate transport vacuum chamber comprising a substrate transfer device, the substrate transfer device configured to detachably couple to the detachable stage and to transfer the substrate supported by the detachable stage in situ between the first v

Abstract: An apparatus for in situ fabrication of multilayer heterostructures is provided comprising a first vacuum chamber adapted for atomic layer deposition and comprising a first stage docking assembly configured to dock a detachable stage configured to support a substrate; a second vacuum chamber adapted for ultra-high vacuum physical or chemical vapor deposition and comprising a second stage docking assembly configured to dock the detachable stage; a load lock vacuum chamber between the first and second vacuum chambers and comprising a third stage docking assembly configured to dock the detachable stage, the load lock vacuum chamber coupled to the first vacuum chamber via a first shared valve and coupled to the second vacuum chamber via a second shared valve; and a substrate transport vacuum chamber comprising a substrate transfer device, the substrate transfer device configured to detachably couple to the detachable stage and to transfer the substrate supported by the detachable stage in situ between the first v

Abstract: A high-sensitivity detector for opto-electronic detection using multiwall carbon nanotubes (MWCNTs) is provided. More specifically, multiwall carbon nanotube films demonstrate an infrared bolometric photoresponse higher than SWCNT films at room temperature. The observed D* exceeding 3.3×106 cm Hz1/2/W with MWCNT-film bolometers and can be further improved to over 1×107 cm Hz1/2/W by adding graphene flakes. The response time of about 1-2 milliseconds with MWCNT bolometers is more than an order of magnitude shorter than that of SWCNT bolometers. For individual MWCNTs with specially designed asymmetric Schottky contacts, one on the sidewall and the other covering the end, the photocurrent has been efficiently harvested and provides a higher detectivity of 6.2×109 cm·Hz1/2/W at room temperature, which is one order of magnitude higher than the convectional VOx detector and makes MWCNT competitive for practical optoelectronic detections over infrared and even longer wavelength range.

Abstract: A high-sensitivity detector for opto-electronic detection using multiwall carbon nanotubes (MWCNTs) is provided. More specifically, multiwall carbon nanotube films demonstrate an infrared bolometric photoresponse higher than SWCNT films at room temperature. The observed D* exceeding 3.3×106 cm Hz1/2/W with MWCNT-film bolometers and can be further improved to over 1×107 cm Hz1/2/W by adding graphene flakes. The response time of about 1-2 milliseconds with MWCNT bolometers is more than an order of magnitude shorter than that of SWCNT bolometers. For individual MWCNTs with specially designed asymmetric Schottky contacts, one on the sidewall and the other covering the end, the photocurrent has been efficiently harvested and provides a higher detectivity of 6.2×109 cm·Hz1/2/W at room temperature, which is one order of magnitude higher than the convectional VOx detector and makes MWCNT competitive for practical optoelectronic detections over infrared and even longer wavelength range.