Patents by Inventor Rongtian Zhang
Rongtian Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9768161Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.Type: GrantFiled: September 17, 2015Date of Patent: September 19, 2017Assignee: QUALCOMM IncorporatedInventors: Rongtian Zhang, Lew Chua-Eoan, Shiqun Gu
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Patent number: 9508607Abstract: Some implementations provide a package that includes a first die and a second die adjacent to the first die. The second die is capable of heating the first die. The package also includes a leakage sensor configured to measure a leakage current of the first die. The package also includes a thermal management unit coupled to the leakage sensor. The thermal management unit configured to control a temperature of the first die based on the leakage current of the first die.Type: GrantFiled: January 15, 2013Date of Patent: November 29, 2016Assignee: QUALCOMM IncorporatedInventors: Lew G. Chua-Eoan, Rongtian Zhang
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Patent number: 9276199Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.Type: GrantFiled: September 26, 2014Date of Patent: March 1, 2016Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
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Publication number: 20160013180Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.Type: ApplicationFiled: September 17, 2015Publication date: January 14, 2016Inventors: Rongtian Zhang, Lew Chua-Eoan, Shiqun Gu
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Patent number: 9202705Abstract: An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.Type: GrantFiled: August 12, 2015Date of Patent: December 1, 2015Assignee: QUALCOMM IncorporatedInventors: Kenneth Kaskoun, Rongtian Zhang, Matthew Michael Nowak, Shiqun Gu
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Patent number: 9142548Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.Type: GrantFiled: September 4, 2012Date of Patent: September 22, 2015Assignee: QUALCOMM IncorporatedInventors: Rongtian Zhang, Lew G. Chua-Eoan, Shiqun Gu
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Patent number: 9138191Abstract: An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.Type: GrantFiled: July 9, 2014Date of Patent: September 22, 2015Assignee: QUALCOMM IncorporatedInventors: Kenneth Kaskoun, Rongtian Zhang, Matthew Michael Nowak, Shiqun Gu
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Patent number: 9136382Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.Type: GrantFiled: August 23, 2013Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Shashank S. Ekbote, Rongtian Zhang
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Publication number: 20150048465Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.Type: ApplicationFiled: September 26, 2014Publication date: February 19, 2015Inventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
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Patent number: 8952504Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.Type: GrantFiled: February 26, 2013Date of Patent: February 10, 2015Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
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Patent number: 8884408Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.Type: GrantFiled: February 26, 2013Date of Patent: November 11, 2014Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
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Publication number: 20140035067Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.Type: ApplicationFiled: August 23, 2013Publication date: February 6, 2014Applicant: Qualcomm IncorporatedInventors: Shashank S. Ekbote, Rongtian Zhang
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Patent number: 8541269Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.Type: GrantFiled: April 29, 2010Date of Patent: September 24, 2013Assignee: QUALCOMM IncorporatedInventors: Shashank S. Ekbote, Rongtian Zhang
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Publication number: 20110266635Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Shashank S. Ekbote, Rongtian Zhang