Patents by Inventor Rongwei Zhang

Rongwei Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079401
    Abstract: In examples, a package comprises first and second dies including first and second diodes, respectively. The package comprises first and second metal contacts coupled to bottom surfaces of the first and second dies, respectively, with the first and second metal contacts exposed to a bottom surface of the package. The package also comprises an isolation layer between the first and second dies and between the first and second metal contacts and a metal layer coupled to top surfaces of the first and second dies. The package also comprises a mold compound covering the first and second dies and the metal layer.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Rongwei ZHANG, Thomas KRONENBERG, Jie CHEN
  • Patent number: 12199008
    Abstract: In examples, a semiconductor package comprises a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; and a semiconductor die having first and second opposing surfaces. The first surface is coupled to the conductive pillar. The package also includes a die attach film abutting the second surface of the semiconductor die and a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film. The metal layer surface is exposed to an exterior of the FCCSP. The package includes a mold compound layer covering the substrate.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 14, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal Mallory Williamson, Rongwei Zhang
  • Publication number: 20240332119
    Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Rongwei Zhang, Woochan Kim, Patrick Francis Thompson
  • Patent number: 12062596
    Abstract: A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 13, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, Chien Hao Wang, Bob Lee
  • Patent number: 12009280
    Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: June 11, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, Woochan Kim, Patrick Francis Thompson
  • Patent number: 11772193
    Abstract: An annular hollow offset-focus laser cladding device, including a housing, a conical reflector arranged in the housing, an annular off-axis parabolic focusing mirror opposite to and arranged coaxially with the conical reflector, a nozzle installed below the conical reflector and a powder-spraying tube connected to a lower end of the nozzle. A top of the housing is provided with a light entrance; the conical reflector faces the light entrance; The powder-spraying tube is coaxial with the annular hollow offset-focusing light reflected by the annular off-axis parabolic focusing mirror; a collimating protective gas jacket is arranged on a periphery of the powder-spraying tube, and the collimating protective gas jacket is located between the annular hollow offset-focused light and the powder-spraying tube; the annular off-axis parabolic focusing mirror is configured to create a horizontally offset of parent parabola focus.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: October 3, 2023
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Tuo Shi, Rongwei Zhang, Geyan Fu, Shihong Shi
  • Publication number: 20230187306
    Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Rongwei Zhang, Woochan Kim, Patrick Francis Thompson
  • Publication number: 20230170282
    Abstract: A semiconductor device includes a silicon die having a first side and a second side, an adhesive layer attached to the first side of the silicon die, and a lead frame. The lead frame comprises a die attach pad having a mounting surface. The mounting surface has a smaller area than an area of the adhesive layer. The silicon die is mounted on the lead frame at the mounting surface so that edges of the silicon die and the adhesive layer overhang the die attach pad without touching the die attach pad. The semiconductor device further includes one or more leads that are spaced apart from the edges of the silicon die and the adhesive layer.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Yuntao Xu, Min Hui Ma, Tiange Xie, Rongwei Zhang
  • Publication number: 20230017286
    Abstract: A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 19, 2023
    Inventors: Rongwei Zhang, Chien Hao Wang, Bob Lee
  • Publication number: 20220371124
    Abstract: A method for realizing high-speed cladding of hollow offset-focus annual laser. The method includes the following steps: dividing laser into annual light, and forming an offset-focus annual light spot after the annual light is focused, which acts on a surface of a matrix; during cladding for the surface of the matrix, selecting laser parameters according to different materials; after every cladding, making a shift by 20-80% of the diameter of the light spot in a vertical direction of a scanning speed of the laser; in the cladding process, selecting shielding gas for protection, and blowing the shielding gas to the molten powder in the air to spray the molten powder in air towards the surface of the matrix at a certain speed so that the cladding layer and the matrix are bonded firmly, and cladding the surface of the matrix to form a coating layer.
    Type: Application
    Filed: April 15, 2022
    Publication date: November 24, 2022
    Applicant: Soochow University
    Inventors: Tuo Shi, Rongwei Zhang, Geyan Fu, Shihong Shi, Yu Wang
  • Publication number: 20220362885
    Abstract: An annular hollow offset-focus laser cladding device, including a housing, a conical reflector arranged in the housing, an annular off-axis parabolic focusing mirror opposite to and arranged coaxially with the conical reflector, a nozzle installed below the conical reflector and a powder-spraying tube connected to a lower end of the nozzle. A top of the housing is provided with a light entrance; the conical reflector faces the light entrance; The powder-spraying tube is coaxial with the annular hollow offset-focusing light reflected by the annular off-axis parabolic focusing mirror; a collimating protective gas jacket is arranged on a periphery of the powder-spraying tube, and the collimating protective gas jacket is located between the annular hollow offset-focused light and the powder-spraying tube; the annular off-axis parabolic focusing mirror is configured to create a horizontally offset of parent parabola focus.
    Type: Application
    Filed: February 17, 2022
    Publication date: November 17, 2022
    Inventors: Tuo SHI, Rongwei ZHANG, Geyan FU, Shihong SHI
  • Publication number: 20220319954
    Abstract: In examples, a semiconductor package comprises a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; and a semiconductor die having first and second opposing surfaces. The first surface is coupled to the conductive pillar. The package also includes a die attach film abutting the second surface of the semiconductor die and a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film. The metal layer surface is exposed to an exterior of the FCCSP. The package includes a mold compound layer covering the substrate.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Jaimal Mallory WILLIAMSON, Rongwei ZHANG
  • Patent number: 11018111
    Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: May 25, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, James Huckabee, Vikas Gupta
  • Publication number: 20210050459
    Abstract: An integrated filter optical package including an ambient light sensor that incorporates an infrared (IR) filter in an integrated circuit (IC) stacked-die configuration is provided. The integrated filter optical package incorporates an infrared (IR) coated glass layer to filter out or block IR light while allowing visible (ambient) light to pass through to a light sensitive die having a light sensor. The ambient light sensor detects an amount of visible light that passes through the IR coated glass layer and adjusts a brightness or intensity of a display screen on an electronic device accordingly so that the display screen is readable.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: Steven Alfred Kummerl, Simon Joshua Jacobs, James Richard Huckabee, Jo Bito, Rongwei Zhang
  • Publication number: 20200381390
    Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.
    Type: Application
    Filed: May 27, 2019
    Publication date: December 3, 2020
    Inventors: Rongwei Zhang, James Huckabee, Vikas Gupta
  • Patent number: 10784188
    Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, Vikas Gupta
  • Patent number: 10727085
    Abstract: A method includes applying a die attach material to a die pad of an integrated circuit package. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit package to mitigate delamination between the integrated circuit die and the die pad.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Rongwei Zhang, Benjamin Stassen Cook, Abram Castro
  • Publication number: 20200185322
    Abstract: In a described example, a packaged device includes a substrate having a device mounting surface with conductive lands having a first thickness spaced from one another on the device mounting surface. A first polymer layer is disposed on the device mounting surface between the conductive lands having a second thickness equal to the first thickness. The conductive lands have an outer surface not covered by the first polymer layer. A second polymer layer is disposed on the first polymer layer, the outer surface of the conductive lands not covered by the second polymer layer. Conductive nanoparticle material is disposed on the outer surface of the conductive lands. A third polymer layer is disposed on the second polymer layer between the conductive nanoparticle material on the conductive lands. At least one semiconductor device die is mounted to the third polymer layer having electrical terminals bonded to the conductive nanoparticle material.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Rongwei Zhang, Vikas Gupta
  • Patent number: 10559524
    Abstract: A packaged semiconductor device includes a leadframe (LF) having a plurality of laminate-supporting pedestals. A cured first die attach (DA) material is on an outer edge of the pedestals being an ultraviolet (UV)-curing DA material having a photoinitiator or a cured B-stage DA material. A cured thermally-curing DA material is on an area of the pedestals not occupied by the UV-curing DA material. A laminate component having bond pads on a top side is mounted top side up on the plurality of pedestals.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: February 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sadia Naseem, Vikas Gupta, Rongwei Zhang
  • Publication number: 20190304881
    Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Rongwei Zhang, Vikas Gupta