Abstract: A polymer binder with high peel strength is used in a secondary lithium battery. The polymer binder is obtained by a ring-opening reaction of polyvinylene carbonate by a nucleophile. The polyvinylene carbonate accounts for 10-90% of the total mass of the polymer binder while the nucleophile accounts for 10-90% of the total mass of the polymer binder. The polymer binder has high peel strength (0.02-0.6 N/mm) and high decomposition voltages (4.5-6.0 V), and can be used as an electrode material binder in a secondary lithium battery.

Abstract: A polymer binder with high peel strength is used in a secondary lithium battery. The polymer binder is obtained by a ring-opening reaction of polyvinylene carbonate by a nucleophile. The polyvinylene carbonate accounts for 10-90% of the total mass of the polymer binder while the nucleophile accounts for 10-90% of the total mass of the polymer binder. The polymer binder has high peel strength (0.02-0.6 N/mm) and high decomposition voltages (4.5-6.0 V), and can be used as an electrode material binder in a secondary lithium battery.

Abstract: The disclosure provides an H2 separation membrane comprised of an alloy having the composition Cu(100-x-y)PdxMy, where x is from about 35 to about 50 atomic percent and where y is from greater than 0 to about 20 atomic percent, and where M consists of magnesium, yttrium, aluminum, titanium, lanthanum, or combinations thereof. The M elements act as strong stabilizers for the B2 phase of the alloy, and extend the critical temperature of the alloy for a given hydrogen concentration and pressure. Due to the phase stabilization and the greater temperature range over which a B2 phase can be maintained, the alloy is well suited for service as a H2 separation membrane, particularly when applicable conditions are established or cycled above about 600° C. over the course of expected operations. In certain embodiments, the B2 phase comprises at least 60 estimated volume percent of the alloy at a steady-state temperature of 400° C. The B2 phase stability is experimentally validated through HT-XRD.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

Abstract: A process is provided for removing resist mask material from a protective barrier layer formed over a layer of low k silicon oxide dielectric material of an integrated circuit structure without damaging the low k dielectric material, and without the necessity of subjecting the exposed via sidewalls of the low k dielectric material to either a pretreatment to inhibit subsequent damage to the low k dielectric material during the resist removal, or a post treatment to repair damage to the low k material after the resist removal. The resist removal process comprises exposing the resist mask material to a hydrogen plasma formed from a source of hydrogen such as ammonia, while maintaining the temperature below about 40° C. to inhibit attack of the low k silicon oxide dielectric material by oxygen released from the decomposition of the resist material.

Abstract: A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.