Patents by Inventor Rongyao Ma
Rongyao Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038837Abstract: A super junction MOSFET device, including: a substrate having a first conductive type; a buffer layer having the first conductive type and disposed on the substrate; a super junction structure disposed on the buffer layer and including multiple first conductive type pillars and multiple second conductive type pillars alternately arranged in a transverse direction, several second conductive type pillars being partially and/or wholly displaced to provide two or more different transverse dimensions for the first conductive type pillars; a body region having the second conductive type and disposed on a top of the second conductive type pillar; a source structure located within the body region and including a source region having the first conductive type and an ohmic contact region having the second conductive type which contacts with the source region; and a gate structure in contact with the first conductive type pillar and the source structure.Type: ApplicationFiled: March 16, 2022Publication date: February 1, 2024Applicant: CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO., LTDInventors: Tian LIAO, Rongyao MA, Daili WANG, Pengcheng ZHANG, Jing LENG, Zhongwang LIU
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Patent number: 9496382Abstract: The present disclosure discloses a field effect transistor (“FET”), a termination structure and associated method for manufacturing. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench and a guard ring region located underneath the bottom of the termination trench in the semiconductor layer. Each termination trench is lined with a termination insulation layer, and is filled with a first conductive spacer and a second conductive spacer respectively against an inner sidewall and an outer sidewall of the termination trench and spaced apart from each other with a space, and a dielectric layer filling the space between the first and the second spacers.Type: GrantFiled: November 21, 2013Date of Patent: November 15, 2016Assignee: CHENGDU MONOLITHIC POWER SYSTEMS CO., LTD.Inventors: Tiesheng Li, Rongyao Ma
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Patent number: 9418983Abstract: A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal.Type: GrantFiled: December 19, 2013Date of Patent: August 16, 2016Assignee: CHENGDU MONOLITHIC POWER SYSTEMS CO., LTD.Inventors: Rongyao Ma, Tiesheng Li
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Patent number: 9362351Abstract: A field effect transistor (“FET”), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.Type: GrantFiled: May 29, 2014Date of Patent: June 7, 2016Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tiesheng Li, Huaifeng Wang
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Patent number: 9281393Abstract: A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device.Type: GrantFiled: March 1, 2013Date of Patent: March 8, 2016Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tiesheng Li, Donald Disney, Lei Zhang
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Patent number: 9230956Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.Type: GrantFiled: October 29, 2013Date of Patent: January 5, 2016Assignee: Chengdu Monolithic Power Systems, Inc.Inventors: Rongyao Ma, Tiesheng Li, Lei Zhang, Daping Fu
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Publication number: 20150249124Abstract: A super junction structural semiconductor device with a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region; trench gate MOSFET units in the first region comprising a plurality of trench gate regions and a first plurality of pillars; a body region between the trench gate regions and the first plurality of pillars; a second plurality of pillars in the second region extending along a corresponding side of the first region comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein in a corner part of the second region, ends of the plurality of lateral pillars and ends of the plurality of longitudinal pillars are stagger and separated apart from each other.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Rongyao Ma, Tiesheng Li, Donald Disney, Lei Zhang
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Publication number: 20150137220Abstract: The present disclosure discloses a field effect transistor (“FET”), a termination structure and associated method for manufacturing. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench and a guard ring region located underneath the bottom of the termination trench in the semiconductor layer. Each termination trench is lined with a termination insulation layer, and is filled with a first conductive spacer and a second conductive spacer respectively against an inner sidewall and an outer sidewall of the termination trench and spaced apart from each other with a space, and a dielectric layer filling the space between the first and the second spacers.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Tiesheng Li, Rongyao Ma
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Patent number: 8969968Abstract: An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.Type: GrantFiled: December 26, 2013Date of Patent: March 3, 2015Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tieshing Li
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Publication number: 20140353748Abstract: A field effect transistor (“FET”), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.Type: ApplicationFiled: May 29, 2014Publication date: December 4, 2014Applicant: Chengdu Monolithic Power Systems, Inc.Inventors: Rongyao Ma, Tiesheng Li, Huaifeng Wang
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Publication number: 20140183639Abstract: An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.Type: ApplicationFiled: December 26, 2013Publication date: July 3, 2014Applicant: Chengdu Monolithic Power Systems, Co., Ltd.Inventors: Rongyao Ma, Tieshing Li
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Publication number: 20140183627Abstract: A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal.Type: ApplicationFiled: December 19, 2013Publication date: July 3, 2014Applicant: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tieshing Li
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Publication number: 20140159143Abstract: A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device.Type: ApplicationFiled: March 1, 2013Publication date: June 12, 2014Applicant: CHENGDU MONOLITHIC POWER SYSTEMS CO., LTD.Inventors: Rongyao Ma, Tiesheng Li, Donald Disney, Lei Zhang
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Patent number: 8735973Abstract: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.Type: GrantFiled: May 2, 2012Date of Patent: May 27, 2014Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Lei Zhang, Donald Ray Disney, Tiesheng Li, Rongyao Ma
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Publication number: 20140117415Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.Type: ApplicationFiled: October 29, 2013Publication date: May 1, 2014Applicant: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tiesheng Li, Lei Zhang, Daping Fu
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Publication number: 20140117416Abstract: A semiconductor device having a trench-gate MOSFET and a vertical JFET formed in a semiconductor layer. In the semiconductor device, a gate region of the vertical JFET may be electrically coupled to a source region of the trench-gate MOSFET, and a drain region of the vertical JFET and a drain region of the trench-gate MOSFET may share a common region in the semiconductor layer.Type: ApplicationFiled: October 31, 2013Publication date: May 1, 2014Inventors: Lei Zhang, Tiesheng Li, Rongyao Ma, Daping Fu
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Publication number: 20140103416Abstract: A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The semiconductor device further includes a semiconductor transistor formed in an active cell area of a substrate. The ESD protection structure is formed atop a termination area of the substrate and is of solid closed shape. The ESD protection structure includes a central doped zone of a first conductivity type and a plurality of second-conductivity-type doped zones and first-conductivity-type doped zones alternately disposed surrounding the central doped zone. The central doped zone occupies substantially the entire portion of the ESD protection structure that is overlapped by a gate metal pad, and is electrically coupled to the gate metal pad. The outmost first-conductivity-type doped zone is electrically coupled to a source metal. The ESD protection structure features a reduced resistance and an improved current uniformity and provides enhanced ESD protection to the transistor.Type: ApplicationFiled: October 10, 2013Publication date: April 17, 2014Applicant: CHENGDU MONOLITHIC POWER SYSTEMS CO., LTD.Inventors: Rongyao Ma, Tiesheng Li, Huaifeng Wang, Heng Li, Fayou Yin
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Patent number: 8680614Abstract: A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode.Type: GrantFiled: June 12, 2012Date of Patent: March 25, 2014Assignee: Monolithic Power Systems, Inc.Inventors: Tiesheng Li, Rongyao Ma, Lei Zhang
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Publication number: 20130328122Abstract: A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: Monolithic Power Systems, Inc.Inventors: Tiesheng Li, Rongyao Ma, Lei Zhang
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Publication number: 20130234245Abstract: A super junction structural semiconductor device with a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region; trench gate MOSFET units in the first region comprising a plurality of trench gate regions and a first plurality of pillars; a body region between the trench gate regions and the first plurality of pillars; a second plurality of pillars in the second region extending along a corresponding side of the first region comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein in a corner part of the second region, ends of the plurality of lateral pillars and ends of the plurality of longitudinal pillars are stagger and separated apart from each other.Type: ApplicationFiled: March 6, 2013Publication date: September 12, 2013Applicant: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tiesheng Li, Donald Disney, Lei Zhang