Abstract: This disclosure is directed to noise mitigation for processing circuitry of an electronic device having a neural network circuit. A neural network circuit may include multiple neural network layers (e.g., a transformer) to perform inference operations. The processing circuitry may include a noise mitigation circuit to reduce a magnitude or magnitude response of noise signals, for example, at one or more frequencies. The noise mitigation circuit may reduce an amplitude of the noise signals by aperiodically providing different clock signals having different clock frequencies to the neural network layers during an inference operation. Alternatively or additionally, the noise mitigation circuit may reduce an amplitude of the noise signals by aperiodically changing clock signal frequencies and supply voltage values of the neural network layers during the inference operation.

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

Abstract: This disclosure is directed to noise mitigation for processing circuitry of an electronic device having a neural network circuit. A neural network circuit may include multiple neural network layers (e.g., a transformer) to perform inference operations. The processing circuitry may include a noise mitigation circuit to reduce a magnitude or magnitude response of noise signals, for example, at one or more frequencies. The noise mitigation circuit may reduce an amplitude of the noise signals by aperiodically providing different clock signals having different clock frequencies to the neural network layers during an inference operation. Alternatively or additionally, the noise mitigation circuit may reduce an amplitude of the noise signals by aperiodically changing clock signal frequencies and supply voltage values of the neural network layers during the inference operation.

Abstract: Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.

Abstract: Systems, methods, and apparatuses disclosed herein can advantageously leverage a power budget to manage heat. These systems, methods, and apparatuses can dynamically distribute the power budget to manage the heat. As part of this dynamic distribution, these systems, methods, and apparatuses can monitor their operation. In some embodiments, when this monitoring indicates that workloads are being created faster than being performed, these systems, methods, and apparatuses can be distributed more of the power budget to optimize the efficiency in performing these workloads. On the other hand, these systems, methods, and apparatuses can be distributed less of the power budget to optimize the efficiency in creating these workloads when this monitoring indicates workloads are being performed faster than being created.

Abstract: The present disclosure describes a system that can include a memory device storing data for operations of a task, a controller to control the operations of the task, and further include a computation engine to perform the computations of the task, where the task can include multiple sets of operations. In some embodiments, the controller can determine an efficiency control metric of a set of operations based on one or more operational parameters of the memory device or the computation engine measured in a time period. Based on the efficiency control metric, the controller can identify that the set of operations of the task is associated with the computation bound phase or the memory bound phase of the task. The controller can adaptively control the computation engine to an efficient operating point to achieve a desired power performance tradeoffs for performing the set of operations of the task.

Abstract: Systems, methods, and apparatuses disclosed herein can advantageously leverage a power budget to manage heat. These systems, methods, and apparatuses can dynamically distribute the power budget to manage the heat. As part of this dynamic distribution, these systems, methods, and apparatuses can monitor their operation. In some embodiments, when this monitoring indicates that workloads are being created faster than being performed, these systems, methods, and apparatuses can be distributed more of the power budget to optimize the efficiency in performing these workloads. On the other hand, these systems, methods, and apparatuses can be distributed less of the power budget to optimize the efficiency in creating these workloads when this monitoring indicates workloads are being performed faster than being created.

Abstract: Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.

Abstract: Systems, methods, and apparatuses disclosed herein can operate in different performance states that provide different energy performance tradeoffs and, in some embodiments, can dynamically switch between these different performance states. These systems, methods, and apparatuses can estimate specific timeframes that workloads are to be completed. These systems, methods, and apparatuses can identify one or more processes that are being executed to perform the workloads. These systems, methods, and apparatuses can dynamically provision one or more performance states from among these different performance states to execute the process to complete the workloads within the specific timeframes. These systems, methods, and apparatuses can dynamically provision the one or more performance states for the one or more process that optimizes power consumption and/or performance while completing the workloads within the specific timeframes.

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics of the first thread can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.