Abstract: A circuit includes a current sensor circuit having inputs and an output. The current sensor inputs are adapted to be coupled to inductor terminals a power converter. The current sensor circuit includes a tunable time constant circuit coupled between the current sensor inputs and the current sensor output. A time constant control circuit is coupled to a tunable time constant circuit, and is configured to tune the time constant circuit responsive to the current sensor output and another signal representative of inductor current. An adjustable gain circuit has a first input coupled to the current sensor output. A direct current resistance (DCR) control circuit has an output coupled to a second input of the adjustable gain circuit, and the DCR control circuit is configured to provide a gain adjust signal at the output thereof responsive to an average current of the inductor and a current command signal for the power converter.

Abstract: In some examples, a converter circuit can be configured to operate in a buck-boost mode. The converter circuit can include a ramp generator that can be configured to generate first and second ramp signals that at least partially overlap respective portions of a buck-boost region during each intermediate clock cycle between clock cycles of a clock signal. By generating the first and second ramp signals during each intermediate clock cycle, first and second drivers can be provided to toggle switches of a power stage, such that an output voltage provided by the power stage can be averaged out over clock cycles of the clock signal to allow for a gradual transition between buck and boost modes of operation of the converter circuit. In some examples, the converter circuit can be configured to operate in a test mode and can be configured to implement trimming of a ramp signal.

Abstract: In some examples, a converter circuit can be configured to operate in a buck-boost mode. The converter circuit can include a ramp generator that can be configured to generate first and second ramp signals that at least partially overlap respective portions of a buck-boost region during each intermediate clock cycle between clock cycles of a clock signal. By generating the first and second ramp signals during each intermediate clock cycle, first and second drivers can be provided to toggle switches of a power stage, such that an output voltage provided by the power stage can be averaged out over clock cycles of the clock signal to allow for a gradual transition between buck and boost modes of operation of the converter circuit. In some examples, the converter circuit can be configured to operate in a test mode and can be configured to implement trimming of a ramp signal.