Abstract: An asynchronous arbiter circuit processes multiple different address signals that request access to the same memory location during the same memroy cycle. The circuit employs two sets of latches. The circuit recognizes access request signals and refresh request signals. For each type of request signal recognized, an associated first latch stores the value of the request signal received, and outputs a first latch output signal. An associated second latch receives the first output latch signal and translates that into a logic state that is long enough to ascertain whether additional request signals have been inputted into the circuit during the memory cycle. A delay element delays one of the request signals received prior to the signals being inputted into the cycle request logic element. The time period of the delay is determined based upon priority accorded to the particular signals.

Abstract: A circuit is provided for testing a plurality of non-readable latch registers. Each of a plurality of first logic gates have an input coupled to one of a plurality of input pins, and an output coupled to an input of each of the latch registers. An address circuit is coupled to the latch registers for selectively addressing one of the latch registers. A plurality of second logic gates each have an input coupled to one output of each of the latch registers and an output coupled to one of the input pins. An enabling circuit is coupled to each of the second logic gates for enabling the logic gates.

Abstract: An interface unit is capable of interfacing a plurality of microprocessor units to a limited number of input/output devices or of interfacing a single microprocessor to a plurality of input/output devices. The interface unit uses a transparent latch to receive the input request. The output of the transparent latch is coupled to an encoder which provides an output to a decoder. The input requests are also coupled to a second encoder which provides an output to a comparator. The comparator compares the outputs between the encoders to determine if a subsequent request of a higher priority is received. If a subsequent request is of a higher priority than the present request being processed the present user will be overruled. One of the main features of the present invention is that the interface unit can operate in an asynchronous mode at a relatively high operating speed.