Patents by Inventor Ronnie M. DE VILLA

Ronnie M. DE VILLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230377896
    Abstract: Disclosed is a plasma diced die from the backside of the wafer using a back surface mask layer. The back surface mask layer remains on the backside of the die, serving as backside protection for the die. The plasma dicing may dice the wafer completely or partially. In the case of partial dicing, the partially diced wafer is expanded to singulate the wafer into individual dies by lateral force.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 23, 2023
    Inventors: Jackson Fernandez Rosario, Enrique E. Sarile Jr, Dzafir Bin Mohd Shariff, Ronnie M. De Villa, Chan Loong Neo, Phongsak Sawasdee
  • Publication number: 20230343668
    Abstract: A semiconductor device has a substrate and a first insulating layer formed over a first major surface of the substrate. A first redistribution layer is formed over the first insulating layer. A second insulating layer is formed over the first redistribution layer. A second redistribution layer can be formed over the second insulating layer, and a third insulating layer can be formed over the second redistribution layer. A protection layer is formed over a second major surface of the substrate for warpage control. A conductive layer is formed over the first redistribution layer, and a bump is formed over the conductive layer. An under bump metallization can be formed under the bump. The protection layer extends over a side surface of the substrate between the first major surface and second major surface. The protection layer further extends over a side surface of the first insulating layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 26, 2023
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Il Kwon Shim, Ronnie M. De Villa, Dzafir Bin Mohd Shariff
  • Publication number: 20230274979
    Abstract: Reliable plasma dicing of a processed wafer with a die attach film (DAF) attached to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. Laser processing is employed to form a modified layer with cracks on a bottom portion of the wafer. Plasma dicing partially dices the processed wafer to about the modified layer. The dicing tape is expanded laterally away from the center of the partially diced processed wafer, singulating it into individual dies. Singulation of the partially plasma diced processed wafer is facilitated by the modified layer.
    Type: Application
    Filed: February 27, 2023
    Publication date: August 31, 2023
    Inventors: Dzafir Bin Mohd Shariff, Enrique E. Sarile, JR., Jackson Fernandez Rosario, Ronnie M. De Villa, Chan Loong Neo, Il Kwon Shim
  • Patent number: 11710661
    Abstract: A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: July 25, 2023
    Assignee: UTAC Headquarters Pte. Ltd
    Inventors: Enrique Jr Sarile, Dzafir Bin Mohd Shariff, Seung Geun Park, Ronnie M. De Villa, Zhong Hai Wang
  • Publication number: 20230178413
    Abstract: Reliable plasma dicing of a wafer with a die attach film (DAF) to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. A combination of plama dicing and laser cutting is employed. Plasma is employed to etch the wafer while laser is employed to cut the DAF.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Dzafir Bin Mohd SHARIFF, IL KWON SHIM, Enrique E. SARILE, JR., Jackson Fernandez ROSARIO, Ronnie M. DE VILLA, Chan Loong NEO
  • Publication number: 20230154796
    Abstract: Reliable plasma dicing of wafers to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer. The patterned passivation stack serves as a plasma dicing mask for plasma dicing the wafer. The sidewalls of the mask openings may be flat or vertical sidewalls. In other cases, the sidewalls of the mask openings are slanted or chamfered sidewalls. The plasma dices the wafer using first and second plasma etch steps. The first plasma etch step etches to form scalloped sidewalls on the first portion of the die and the second plasma step etches to form flat or vertical sidewalls on a second portion of the die. The second portion of the die is the lower portion of the substrate or wafer. This prevents backside notching to improve reliability.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 18, 2023
    Inventors: Dzafir Bin Mohd Shariff, Enrique E. Sarile, JR., Jackson Fernandez Rosario, Ronnie M. De Villa, Chan Loong Neo
  • Publication number: 20230154795
    Abstract: The present disclosure relates to plasma dicing of wafer. More specifically, the present disclosure is directed to frame masks and methods for plasma dicing wafers utilizing frame masks. The frame mask includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 18, 2023
    Inventors: Dzafir Bin Mohd Shariff, IL KWON SHIM, Enrique Jr Sarile, Jackson Fernandez Rosario, Ronnie M. De Villa, Chan Loong Neo
  • Publication number: 20210118738
    Abstract: A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 22, 2021
    Inventors: Enrique Jr SARILE, Dzafir Bin Mohd SHARIFF, Seung Geun PARK, Ronnie M. DE VILLA, Zhong Hai WANG