Abstract: A method and circuit control the value of generated voltage derived from a supply voltage as the value of the supply voltage varies, such as during burn-in of an integrated circuit. A voltage generation circuit includes a generator circuit that receives a supply voltage and has a reference node and develops an output voltage from the supply voltage, the output voltage having a value that is a function of a reference voltage applied on the reference node. A coupling circuit receives the supply voltage and operates in response to a voltage control signal to vary an electronic coupling of the supply voltage to the reference node to thereby adjust the value of the reference voltage. A voltage sensing circuit develops the voltage control signal that is applied to the coupling circuit in response to the reference voltage.

Abstract: A data receiver circuit uses two parallel differential circuits to process incoming data signals. The parallel differential circuits each compare the data signal to a different clock signal. In one embodiment, the clock signals are complementary signals. Further, the parallel differential circuits are coupled to control a current mirror circuit such that an output of the data receiver is controlled in response to a differential transition between the data signal and one of the complementary clock signals. In one embodiment, a first differential circuit includes a transistor controlled by a CLK signal and a transistor controlled by the Data signal. The second differential circuit includes a transistor controlled by a /CLK signal (complement of CLK) and a transistor controlled by the Data signal.

Abstract: The invention is a method and circuitry for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage it is advantageous to cross-connect every x stages of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines of the present invention are also disclosed.

Abstract: A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digital signal is stored in an associated storage circuit and defines a timing offset between the corresponding digital signal and the clock. The clock is output along with each digital signal having the timing offset defined by the corresponding phase command and the digital signals are captured responsive to the clock and evaluated to determine if each digital signal was successfully captured. A phase adjustment command adjusts the value of each phase command. These operations are repeated for a plurality of phase adjustment commands until respective final phase commands allowing all digital signals to be successfully captured is determined and stored in the storage circuits.

Abstract: A data receiver circuit uses two parallel differential circuits to process incoming data signals. The parallel differential circuits each compare the data signal to a different clock signal. In one embodiment, the clock signals are complementary signals. Further, the parallel differential circuits are coupled to control a current mirror circuit such that an output of the data receiver is controlled in response to a differential transition between the data signal and one of the complementary clock signals. In one embodiment, a first differential circuit includes a transistor controlled by a CLK signal and a transistor controlled by the Data signal. The second differential circuit includes a transistor controlled by a /CLK signal (complement of CLK) and a transistor controlled by the Data signal.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A leadframe is disclosed comprising a plurality of leads. The leads of the leadframe extend radially from a first end to a second end such that a portion of each lead has a generally arcuate shape. The first end is for coupling with a printed circuit board. The second end is for coupling the a semiconductor die. Alternatively, the leads have a plurality of segments. Each lead has at least three segments disposed between the first end and the second end. The segments forming the leads are disposed such that each lead generally has an arcuate shape. The segments each have substantially the same length, or can have varying lengths. An integrated circuit package is also disclosed including a leadframe having a plurality of leads, at least one semiconductor die coupled with the leads, and an insulating enclosure encapsulating the die and a portion of the leadframe. The leads each extend radially from a first end to a second end such that each lead has a generally arcuate shape.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A leadframe with a plurality of leads. The leads of the leadframe extend radially from a first end to a second end such that a portion of each lead has a generally arcuate shape. The first end is for coupling with a printed circuit board. The second end is for coupling the a semiconductor die. Alternatively, the leads have a plurality of segments. Each lead has at least three segments disposed between the first end and the second end. The segments forming the leads are disposed such that each lead generally has an arcuate shape. The segments each have substantially the same length, or can have varying lengths. An integrated circuit package is also disclosed including a leadframe having a plurality of leads, at least one semiconductor die coupled with the leads, and an insulating enclosure encapsulating the die and a portion of the leadframe. The leads each extend radially from a first end to a second end such that each lead has a generally arcuate shape.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: In digital circuits, such as memory circuits, it is sometimes necessary to delay one signal a precise amount of time relative a reference signal. One way to do this is to feed the reference signal to a delay-locked loop which generates a set of signals, each delayed a different amount relative the reference signal. However, as circuits get faster and faster, conventional delay-locked loops require the addition of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal.

Abstract: A loss of signal detector for use with a delay-locked loop of the type which produces a plurality of output signals in response to a clock signal, is comprised of a first monitor for receiving a first one of the plurality of output signals from the delay-locked loop. The second monitor receives a second one of the plurality of output signals from the delay-locked loop. The first and second signals are preferably, but not necessarily, in quadrature with respect to one another. Each of the monitors is clocked with a clock signal and the inverse of the clock signal. A plurality of logic gates is responsive to the first and second monitors for producing an output signal.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.

Abstract: A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the plurality of signals for producing at least one clock signal in response to control signals input to the plurality of multiplexers. A clock driver is provided for driving the clock signal. A variable delay circuit is positioned to delay the external clock signal before input to the delay-locked loop. A compound feedback loop is responsive to certain of the plurality of signals for producing a control signal input to the variable delay circuit.