Abstract: An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.

Abstract: An enhanced digital signal processor (EDSP) includes execution section that includes the following constituents: a processor, an arithmetic logic unit (ALU), a memory device for holding set of instructions for execution selected from enhanced set of instructions, a memory device for holding data, another clock generator for generating a plurality of clock signals coupled to above constituents. Internal communication bus coupled to the above constituents for affording controlled communication between them, a correlator, coupled to the bus, for communication with the execution section. The correlator having an input port for receiving external input data and an output port for outputting data.