Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.

Abstract: Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: A test generator generating a test for a system having a plurality of executing entities that are capable of concurrent execution, the test comprises transactions that comprise one or more access transactions that are configured to access a shared resource and one or more reconfiguration transactions configured that are configured to reconfigure the shared resource, wherein said generating comprises: determining a partial order between pairs of transactions that are both associated with the shared resource and that at least one of which is a reconfiguration transaction; and generating the test so as to enforce the partial order during execution of the test by the system.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: A test generator generating a test for a system having a plurality of executing entities that are capable of concurrent execution, the test comprises transactions that comprise one or more access transactions that are configured to access a shared resource and one or more reconfiguration transactions configured that are configured to reconfigure the shared resource, wherein said generating comprises: determining a partial order between pairs of transactions that are both associated with the shared resource and that at least one of which is a reconfiguration transaction; and generating the test so as to enforce the partial order during execution of the test by the system.

Abstract: A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

Abstract: A method, apparatus, and product for partial instruction-by-instruction checking on acceleration platforms. The method comprising: obtaining a trace from an hardware accelerator, wherein the trace is generated by the hardware accelerator during simulation of an execution of a test case on a circuit design; identifying a synchronization point in the trace; simulating execution of the test case by a reference model until reaching the synchronization point; and performing instruction-by-instruction checking in order to identify an error in the circuit design based on the simulated execution by the hardware accelerator, wherein the instruction-by-instruction checking is performed with respect to a portion of the trace that relates to operation after executing the synchronization point, wherein the instruction-by-instruction checking utilizes the reference model to determine an expected outcome of each event recorded in the portion of the trace.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.

Abstract: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.

Abstract: Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions.

Abstract: A method of automatically defining a new class in a class hierarchy includes creating a descendent class that descends from one or more specified ancestor classes; sequentially analyzing each class along each inheritance path from the specified ancestor classes to a specified similar class to identify each class item in each class that is not selected from the specified ancestor classes; storing a respective pointer for each class item identified in each class that is not inherited by the class referencing the class item and associated with the class; storing a respective pointer for each class item identified in each class that is inherited and redefined by the class referencing the class item and being associated with the class if a pointer referencing the class item is not already stored; and copying each class item referenced by a stored pointer to the descendent class.

Abstract: A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

Abstract: Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions.

Abstract: A method of automatically defining a new class in a class hierarchy includes creating a descendent class that descends from one or more specified ancestor classes; sequentially analyzing each class along each inheritance path from the specified ancestor classes to a specified similar class to identify each class item in each class that is not selected from the specified ancestor classes; storing a respective pointer for each class item identified in each class that is not inherited by the class referencing the class item and associated with the class; storing a respective pointer for each class item identified in each class that is inherited and redefined by the class referencing the class item and being associated with the class if a pointer referencing the class item is not already stored; and copying each class item referenced by a stored pointer to the descendent class.

Abstract: The invention provides a computer-implemented method for generating a solution to a constraint satisfaction problem (CSP). The method operates to implement various steps that include defining the CSP problem by a set of variable having finite domains, and constraints defined over the variables, solving the CSP by assigning values to said variables that are consistent with the constraints and debugging the CSP solution. The debugging of the CSP solution is carried out by iteratively executing a propagator to reduce the variable domain. Augmenting the constraints is carried out to supply an explanation for particular values assigned to the variables, and constraints defined over the variable utilized in the solution.