Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

Abstract: A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation.

Abstract: A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation.

Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Abstract: An adaptation of the sum-of-absolute-differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first and second operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU), and a destination register. An add/subtract enable input on the ALU receives a most significant bit (MSB) of the second set of binary data. The ALU adds the first and second data sets if the MSB is a “0” and subtracts the second data set from the first data set if the MSB is a “1.” The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.

Abstract: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.

Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Abstract: A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.

Abstract: An adaptation of the sum-of-absolute-differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first and second operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU), and a destination register. An add/subtract enable input on the ALU receives a most significant bit (MSB) of the second set of binary data. The ALU adds the first and second data sets if the MSB is a “0” and subtracts the second data set from the first data set if the MSB is a “1.” The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.

Abstract: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.

Abstract: A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.