Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.

Abstract: In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.

Abstract: A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.

Abstract: The operating rate of an electronic system is maximized without exceeding a thermal constraint, such as a maximum junction temperature of an integrated circuit (IC) or other portion of the electronic system. An operating parameter of the system that controls the thermal output of the system is calculated for an upcoming time period based upon the previously measured thermal performance relationship to the operating parameter level. If the predicted thermal performance will exceed a maximum allowable level of the thermal constraint, then the operating parameter is reduced by an amount calculated to keep the thermal constraint at a level just below the maximum allowable level, thus resulting in an optimal control approach to maximizing the system performance while not exceeding the thermal constraint.

Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.

Abstract: A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.

Abstract: A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP table includes a plurality of PIP information fields and the next value table includes a plurality of fields. The multi-mode predictor also includes a plurality of prediction modes. The processor includes a set of instructions that index the PIP table to provide a valid signal. The processor also includes a set of predicted values for the set of instructions. The set of predicted values is stored in the PIP table and the next value table. According to the valid signal a hit/miss condition in the next value table, a predicted value is selected from the PIP table or the next value table.

Abstract: In one embodiment, the present invention includes a method for protecting a value to be stored in a register of a register file with a first level of protection if the value is predicted to be used for a first time period, and protecting the value with a second level of protection if the value is predicted to be used for a second time period. Other embodiments are described and claimed.

Abstract: The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

Abstract: A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number of accesses to the trace.

Abstract: The operating rate of an electronic system is maximized without exceeding a thermal constraint, such as a maximum junction temperature of an integrated circuit (IC) or other portion of the electronic system. An operating parameter of the system that controls the thermal output of the system is calculated for an upcoming time period based upon the previously measured thermal performance relationship to the operating parameter level. If the predicted thermal performance will exceed a maximum allowable level of the thermal constraint, then the operating parameter is reduced by an amount calculated to keep the thermal constraint at a level just below the maximum allowable level, thus resulting in an optimal control approach to maximizing the system performance while not exceeding the thermal constraint.

Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.

Abstract: Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.

Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

Abstract: A processor having a register renaming structure and method is disclosed to recover a free list. The processor includes a physical register file including physical registers. The processor also includes a decoder to decode an instruction to indicate a destination logical register. The processor also includes a register allocation table to map the destination logical register to an allocated physical register. The processor also includes an active list that includes an old field and a new field. The old field includes at least one evicted physical register from the register alias table. The new field includes the allocated physical register. The processor also includes the free list of unallocated physical registers reclaimed from the active list.

Abstract: Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.

Abstract: Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.

Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.