Patents by Inventor Ronny Schneider
Ronny Schneider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240028450Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.Type: ApplicationFiled: June 23, 2023Publication date: January 25, 2024Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
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Patent number: 11870616Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.Type: GrantFiled: January 25, 2021Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Stefan Dietrich, Natalija Jovanovic, Ronny Schneider, Martin Brox, Thomas Hein, Michael Dieter Richter
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Patent number: 11726865Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.Type: GrantFiled: April 21, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
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Publication number: 20230188248Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Inventors: Stefan Dietrich, Thomas Hein, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter, Martin Brox
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Patent number: 11621033Abstract: Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.Type: GrantFiled: January 8, 2021Date of Patent: April 4, 2023Assignee: Micron Technology, Inc.Inventors: Martin Brox, Thomas Hein, Stefan Dietrich, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter
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Patent number: 11601215Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.Type: GrantFiled: January 14, 2021Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventors: Stefan Dietrich, Thomas Hein, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter, Martin Brox
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Publication number: 20220245026Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
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Patent number: 11327832Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.Type: GrantFiled: January 15, 2021Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
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Publication number: 20210234732Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.Type: ApplicationFiled: January 25, 2021Publication date: July 29, 2021Inventors: Stefan Dietrich, Natalija Jovanovic, Ronny Schneider, Martin Brox, Thomas Hein, Michael Dieter Richter
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Publication number: 20210226722Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.Type: ApplicationFiled: January 14, 2021Publication date: July 22, 2021Inventors: Stefan Dietrich, Thomas Hein, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter, Martin Brox
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Publication number: 20210224149Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.Type: ApplicationFiled: January 15, 2021Publication date: July 22, 2021Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
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Publication number: 20210217458Abstract: Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.Type: ApplicationFiled: January 8, 2021Publication date: July 15, 2021Inventors: Martin Brox, Thomas Hein, Stefan Dietrich, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter
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Patent number: 10371745Abstract: To include in a device a controller to control operation of the device in a normal-operation mode and in a test mode for performing one or more tests including an accelerated aging test, a temperature sensor to measure operating temperature of the device, and an overheat protection circuit to prevent overheating of the memory device during the test mode. With this overheat protection circuit, a device may undergo an efficient and reliable accelerated aging test with reduced or non-existent, possibility of suffering an overheat damage.Type: GrantFiled: January 23, 2014Date of Patent: August 6, 2019Assignee: Micron Technology, Inc.Inventors: Ronny Schneider, Martin Brox, Juan-Antonio Ocon-Garrido
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Publication number: 20150204941Abstract: To include in a device a controller to control operation of the device in a normal-operation mode and in a test mode for performing one or more tests including an accelerated aging test, a temperature sensor to measure operating temperature of the device, and an overheat protection circuit to prevent overheating of the memory device during the test mode. With this overheat protection circuit, a device may undergo an efficient and reliable accelerated aging test with reduced or non-existent, possibility of suffering an overheat damage.Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Inventors: Ronny SCHNEIDER, Martin BROX, Juan-Antonio OCON-GARRIDO
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Patent number: 8918597Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.Type: GrantFiled: August 29, 2008Date of Patent: December 23, 2014Assignee: Infineon Technologies AGInventors: Martin Brox, Ronny Schneider
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Patent number: 8773165Abstract: Disclosed herein is a logic circuit that includes a transistor T1 coupled between VPERI and a node n1, a transistor T2 coupled between VPERI and a node n2, a transistor T3 coupled between VSS and a node n3, a transistor T4 coupled between VSS and a node n4, transistors T5 and T7 coupled in series between the nodes n1 and n3, transistors T9 and T11 coupled in series between the nodes n1 and n3, transistors T6 and T8 coupled in series between the nodes n2 and n4, and transistors T10 and T12 coupled in series between the nodes n2 and n4. An output signal Y is output from a connection point of the transistors T5 and T7 and a connection point of the transistors T6 and T8.Type: GrantFiled: September 28, 2012Date of Patent: July 8, 2014Inventors: Yuki Nakamura, Chiaki Dono, Ronny Schneider
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Publication number: 20100052729Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Inventors: Martin Brox, Ronny Schneider
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Publication number: 20060117201Abstract: A variable pipeline comprises a first pipeline element configured to latch a first signal in response to a first edge of a clock signal to provide a second signal, a selection circuit configured to select the second signal and pass the second signal to provide a third signal, and a second pipeline element configured to latch the third signal in response to a second edge of the clock signal to provide a fourth signal.Type: ApplicationFiled: November 30, 2004Publication date: June 1, 2006Inventor: Ronny Schneider
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Patent number: 6975238Abstract: A circuit and method for detecting soft errors produced in latches. An exemplary embodiment of a circuit includes a block of concatenated latches, each latch having a comparator, with an output from the final latch comparator representing a parity bit for the latch block. The circuit further includes a element to store the block parity bit, and a comparator for the block parity bit and stored parity bit. A latch soft error is detected by monitoring an output from the parity bit comparator, which signals an error when the latch block parity bit changes state.Type: GrantFiled: October 1, 2003Date of Patent: December 13, 2005Assignee: Infineon Technologies AGInventor: Ronny Schneider
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Publication number: 20050073345Abstract: A circuit and method for detecting soft errors produced in latches. An exemplary embodiment of a circuit includes a block of concatenated latches, each latch having a comparator, with an output from the final latch comparator representing a parity bit for the latch block. The circuit further includes a element to store the block parity bit, and a comparator for the block parity bit and stored parity bit. A latch soft error is detected by monitoring an output from the parity bit comparator, which signals an error when the latch block parity bit changes state.Type: ApplicationFiled: October 1, 2003Publication date: April 7, 2005Inventor: Ronny Schneider