Abstract: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit. The processing stage has inputs and outputs and includes circuit components arranged so as to define multiple logical paths between the inputs and the outputs. A timing constraint to be applied in splitting the processing stage into multiple sub-stages is specified. At least one of the logical paths is identified as a false path, to which the timing constraint is not to apply. The design is modified responsively to the timing analysis, to the timing constraint, and to identification of the false path, so as to split the processing stage into the sub-stages.