Abstract: A processor prefetches instructions in a pipelined manner from a first (L1) cache to a local instruction cache, with an instruction pointer device being utilized to select one of a plurality of incoming addresses for fetching purposes. Instructions returned from the L1 cache are stored in an instruction streaming buffer before they are actually written into the instruction cache. A way multiplexer outputs instructions to dispersal logic in the processor, and is fed by either the local cache or a bypass path that provides the instruction to the way multiplexer from a plurality of bypass sources, which includes the instruction streaming buffer. A request address buffer registers physical and virtual addresses associated with an instruction of a miss request by the processor to the L1 cache. Each entry of the request address buffer has an ID that is sent to the L1 cache with the miss request.

Abstract: A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.