Abstract: A master device issues memory burst transaction requests via an interconnection bus to fetch data from a slave device. A cipher engine is coupled to the interconnection bus and decrypts the fetched data to produce plaintext data for the master device. The cipher engine selectively operates according to a stream cipher operation mode, or a block cipher operation mode. The cipher engine is configured to stall a read data channel of the interconnection bus between the slave device and the master device in response to the cipher engine switching from the block cipher operation mode to the stream cipher operation mode. The read data channel is reactivated in response to a last beat of a read burst of the plaintext data produced by the cryptographic engine.

Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.

Abstract: A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.

Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.

Abstract: A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.

Abstract: A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by: maintaining the in a stand-by mode when no memory read/write commands are to be executed, and if any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.

Abstract: A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.

Abstract: A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by: maintaining the in a stand-by mode when no memory read/write commands are to be executed, and if any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.

Abstract: A low area architecture for embedded programming flash memory portions in microcontrollers is based on substitution of the ROM/RAM/CORE functionality with a digital ISP controller implemented in a finite state machine and a standard interface. After connecting ports of the embedded programming flash memory portion and releasing a RESET pin, the microcontroller enters a particular operating mode and is managed by the digital ISP controller instead of the CORE. The ROM is not required to set up the microcontroller, and as a consequence, transfer of the boot program from the ROM to the RAM is not requested for subsequent execution.

Abstract: A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.