Abstract: An improved ESD cell provides in the worst case 2,000 volts HBM ESD protection using an NMOS transistor in a lightly-doped drain process. An NMOS transistor has its source connected to ground, and its drain connected through a polysilicon resistor to a pad of an integrated circuit. The pad is also connected by metal to an n+ pocket tap of an n-type epitaxial layer formed on a p-type substrate. The connection of pad metal to the pocket tap forms a second parasitic lateral bipolar junction transistor (BJT) having as a base the p-type well, having an emitter the source of the NMOS transistor, and having as its collector the pocket tap. The parasitic transistor turns on at the right moment and is able to shunt more current around the polysilicon resistor, thus giving a dramatic increase in ESD protection. In a worst case, the ESD cell can pass at a minimum of 2,000 volts, and the expected range of HBM ESD values is between 2,500 volts and 3,000 volts depending upon process variations.

Abstract: An RF matching network provides matching between a charged first transmission line and a relay circuit which is switched to connect the charged transmission line to one end of a second transmission line to generate a high-voltage, high-current test pulse for a DUT connected to the other end of the second transmission line. A low pass filter section of the RF matching network suppresses transient and ringing signals which might pass through the parasitic capacitance of the relay circuit and which trigger the prematurely trigger the DUT. To remove residual charge after discharging the first transmission line, the transmission line is grounded with a GND relay before leakage tests are conducted to prevent electrically stress of destruction of leakage testing circuitry if the residual charge is not dissipated before testing for leakage.

Abstract: System and method for optimizing the structure of a transistor to withstand electrostatic discharge by quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment is a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.

Abstract: A pulse discharge circuit for pulse testing an integrated-circuit device under test (DUT) is provided which uses three separate switching relays S1, S2, and S3, which are operated in a predetermined sequence. For charging the capacitance of a pulse-forming transmission line, the relay contact of S1 is closed while the relay contacts of relays S2, S3 are both open. For discharging the charge on the transmission line to form a test pulse, the relay contact of S1 is first opened, and the relay contact of S2 is then closed while the relay contact of S3 is open. After each test pulse is generated and applied to a DUT, the condition of the DUT is determined by a leakage current measurement. The relay contact S2 is opened to isolate the pulse generator circuit and then the relay contact S3 is closed.

Abstract: The present invention relates to a system and method of quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment comprises a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.