Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Abstract: A method for managing a flash memory device including pages of memory cells is described. The memory device may be erasable at the page level, and the pages may include operative pages for storing operative values and service pages for storing information relating to the erasing of the operative pages. In response to a request to erase selected operative pages, the method may include determining a service page in use among the service pages according to service information stored in the service pages, verifying the presence a service page to be erased, and applying an erasing pulse to each service page to be erased. The method may also include writing an address of the operative pages into the service page in use, erasing the selected operative pages, and writing a completion indication of the erasing of the selected operative pages into the service page in use.

Abstract: A bandgap voltage reference circuit for generating a bandgap voltage reference. An embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. The circuit further comprises an operational amplifier having a first input coupled to the first circuit element and a second input coupled to the second reference circuit element. The circuit also comprises a control circuit comprising first capacitive element and second capacitive element.

Abstract: An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition.

Abstract: A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.

Abstract: A method for managing a flash memory device including pages of memory cells is described. The memory device may be erasable at the page level, and the pages may include operative pages for storing operative values and service pages for storing information relating to the erasing of the operative pages. In response to a request to erase selected operative pages, the method may include determining a service page in use among the service pages according to service information stored in the service pages, verifying the presence a service page to be erased, and applying an erasing pulse to each service page to be erased. The method may also include writing an address of the operative pages into the service page in use, erasing the selected operative pages, and writing a completion indication of the erasing of the selected operative pages into the service page in use.

Abstract: An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current.

Abstract: An embodiment of a circuit is described for the generation of a temperature-compensated voltage reference of the type comprising at least one generator circuit of a band-gap voltage, inserted between a first and a second voltage reference and including an operational amplifier, having in turn a first and a second input terminal connected to an input stage connected to these first and second input terminal and comprising at least one pair of a first and a second bipolar transistor for the generation of a first voltage component proportional to the temperature.

Abstract: An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition.

Abstract: An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current.

Abstract: An embodiment of a bandgap voltage reference circuit for generating a bandgap voltage reference. Said embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. Said circuit further comprises a third reference circuit element for receiving a third current corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier.

Abstract: An embodiment of a circuit is described for the generation of a temperature-compensated voltage reference of the type comprising at least one generator circuit of a band-gap voltage, inserted between a first and a second voltage reference and including an operational amplifier, having in turn a first and a second input terminal connected to an input stage connected to these first and second input terminal and comprising at least one pair of a first and a second bipolar transistor for the generation of a first voltage component proportional to the temperature.