Patents by Inventor Roseanne Duca
Roseanne Duca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240132340Abstract: A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: STMicroelectronics (Malta) Ltd.Inventor: Roseanne DUCA
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Publication number: 20240038610Abstract: A method of manufacturing a semiconductor package with an one or more dice present within a transparent resin, which may be an epoxy-based transparent resin or a silicone-based transparent resin, includes coupling the one or more dice to respective surfaces of a plurality of base portions of a panel substrate. Each one of the respective surfaces is between ones of a plurality of walls of the panel substrate that protrude from the respective surfaces of the panel substrate. A plurality of wirebonds may be formed to provide electrical pathways between the one or more dice and conductive structures of the panel substrate accessible at the respective surfaces of the panel substrate. A transparent resin may be formed to fill recesses or cavities between ones of the plurality of walls, and the panel substrate may then be singulated along the plurality of walls.Type: ApplicationFiled: July 20, 2023Publication date: February 1, 2024Applicant: STMICROELECTRONICS (MALTA) LTDInventor: Roseanne DUCA
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Publication number: 20230046645Abstract: A support substrate includes an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer. A back side of an integrated circuit chip is mounted to an upper surface of the support substrate at a die attach location. The upper surface of the support substrate includes a cavity located within the die attach location, where the cavity extends under the back side of the integrated circuit chip. The cavity is defined by an area where the solder mask layer and at least a portion of the electrically conductive layer have been removed. Bonding wires connect connection pads on a front side of the integrated circuit chip to connection pad on the upper surface of the support substrate.Type: ApplicationFiled: July 21, 2022Publication date: February 16, 2023Applicant: STMicroelectronics (Malta) Ltd.Inventor: Roseanne DUCA
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Publication number: 20230005755Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.Type: ApplicationFiled: September 12, 2022Publication date: January 5, 2023Applicants: STMicroelectronics S.r.l., STMicroelectronics (MALTA) LtdInventors: Roseanne DUCA, Dario PACI, Pierpaolo RECANATINI
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Patent number: 11443958Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.Type: GrantFiled: December 1, 2020Date of Patent: September 13, 2022Assignees: STMicroelectronics S.r.l., STMicroelectronics (Malta) LtdInventors: Roseanne Duca, Dario Paci, Pierpaolo Recanatini
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Publication number: 20210166949Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.Type: ApplicationFiled: December 1, 2020Publication date: June 3, 2021Applicants: STMicroelectronics S.r.l., STMicroelectronics (Malta) LtdInventors: Roseanne DUCA, Dario PACI, Pierpaolo RECANATINI
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Patent number: 10892201Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: GrantFiled: February 12, 2020Date of Patent: January 12, 2021Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome Lopez, Roseanne Duca
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Publication number: 20200185288Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: ApplicationFiled: February 12, 2020Publication date: June 11, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome LOPEZ, Roseanne DUCA
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Patent number: 10600704Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: GrantFiled: September 17, 2018Date of Patent: March 24, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome Lopez, Roseanne Duca
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Publication number: 20190088562Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: ApplicationFiled: September 17, 2018Publication date: March 21, 2019Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome LOPEZ, Roseanne DUCA
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Patent number: 9620438Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.Type: GrantFiled: February 6, 2015Date of Patent: April 11, 2017Assignees: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTDInventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
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Patent number: 9449912Abstract: An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE.Type: GrantFiled: June 11, 2015Date of Patent: September 20, 2016Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (MALTA) LTDInventors: Xueren Zhang, Kim-Yong Goh, Roseanne Duca
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Patent number: 9257372Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.Type: GrantFiled: September 19, 2013Date of Patent: February 9, 2016Assignees: STMicroelectronics (Mala) Ltd, STMicroelectronics Pte LtdInventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
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Publication number: 20150235929Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.Type: ApplicationFiled: February 6, 2015Publication date: August 20, 2015Applicants: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTDInventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
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Publication number: 20140091443Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.Type: ApplicationFiled: September 19, 2013Publication date: April 3, 2014Applicants: STMicroelectronics Pte Ltd, STMicroelectronics (Malta) LtdInventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa