Abstract: A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.

Abstract: A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.

Abstract: A process is disclosed for forming multilayered polyimide structure from negative photosensitive polyimide precursors. An initial polyimide layer is deposited and imagewise exposed. The unexposed portions of the initial polyimide layer are inhibited and then a second polyimide layer is deposited and likewise imagewise exposed. The films are developed, thereby forming a multilayer polyimide structure. After formation of the multilayer polyimide structure, a conductive material is applied on a substrate and then the polyimide layers are lifted off thereby forming a desired pattern of metallization.

Abstract: A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced.

Abstract: Novel intermediate compounds capable of being applied to a semiconductor precursor by spin-on methods which exhibit good planarity and gap-fill characteristics, the cured composites of which are capable of withstanding temperatures in excess of 500.degree. C. The disclosure further encompasses a process for fabricating semiconductor devices utilizing the intermediate compounds and its composite.