Patents by Inventor Roshan WEERASEKERA

Roshan WEERASEKERA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package and method of forming the same
    Patent number: 11018080
    Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of first layer contact elements on a first side and a plurality of second layer contact elements on a second side opposite the first side, and a first semiconductor die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may further include a second semiconductor die including a plurality of second electrical die contact elements coupled to the plurality of second layer contact elements, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact elements.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 25, 2021
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Roshan Weerasekera, Surya Bhattacharya, Ka Fai Chang, Vempati Srinivasa Rao
  • SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
    Publication number: 20190043792
    Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of first layer contact elements on a first side and a plurality of second layer contact elements on a second side opposite the first side, and a first semiconductor die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may further include a second semiconductor die including a plurality of second electrical die contact elements coupled to the plurality of second layer contact elements, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact elements.
    Type: Application
    Filed: March 17, 2017
    Publication date: February 7, 2019
    Inventors: Roshan WEERASEKERA, Surya BHATTACHARYA, Ka Fai CHANG, Vempati Srinivasa RAO