Abstract: A method and apparatus for marking a region of source code within a program unit and extracting an executable version of this marked region of code. The executable version has a initialized program state equivalent to that of the original source code when the original source code entered the region. The method and apparatus remove as much source code as possible from the original source code while retaining enough code to enable the extracted region execute (replay) in a manner identical to the execution of the program region in the context of the original system.

Abstract: A system and method of generating object code from an intermediate representation of source code is described. The intermediate representation includes a plurality of basic blocks each being represented by a plurality dam dependency graphs, wherein each data dependency graph comprises a plurality of nodes each corresponding to an instruction from the target computer instruction set. The present invention operates by selecting a source basic block (that is one of the basic blocks of the intermediate representation) and a target basic block (that is another of the basic blocks of the intermediate representation), and by identifying a maximal set of instructions contained in the source basic block that are movable from the source basic block to the target basic block without violating any data dependency relationships of the data dependency graphs. An overall cost model of aggregately moving instructions of the maximal set from the source basic block to the target basic block is generated.

Abstract: A horizontal computer for execution of an instruction loop with a branch. The computer includes parallel processors, a multiconnect unit for storing operands for the processors, and instruction unit for specifying address offsets and operations to be performed by the processors, and an invariant address unit for combining the address offsets with a modifiable pointer to form source and destination addresses in the multiconnect unit. The instruction unit enables different ones of the processors both as a function of whether a branch instruction is to be executed and as a function of which iteration of the loop is being executed. The processors are enabled by processor control circuitry or by selectively providing instructions to the processors so that different operations are performed during different iterations.

Abstract: A horizontal architecture computer in which a plurality of instructions are selectively communicated to a processing unit simultaneously or sequentially. The computer includes a processing unit with a plurality of processors, an instruction unit with a plurality of storage locations for storing instructions, and means for communicating the instructions to the processors. A first connection circuit provides a plurality of parallel communication channels between the storage locations and the processors and a second connection circuit provides a single serial communication channel between the storage locations and the processors. The first circuit is selected if a multioperation instruction is to be executed, otherwise the second circuit is selected instead.

Abstract: A horizontal computer for executing a loop with recurrence. The computer features a horizontal architecture in which parallel processors repeatedly iterate a loop of instructions with recurrence, that is, where a result operand from one iteration is used as a source operand in a later iteration. Some of the processors provide result operands and some perform operations on source operands. A multiconnect register stores the operands at addressable locations. An instruction unit counts iterations and gives source and result address offsets relative to a modifiable pointer. An invariant address unit assigns a value to the modifiable pointer according to which iteration is being performed and combines the pointer with the offsets to provide source and destination addresses. An epilog counter stores a count of ending iterations in which progressively fewer instructions are executed in each succeeding iteration.

Abstract: A horizontal computer for execution of an instruction loop with overlapped code. The computer includes a plurality of processors, a multiconnect unit for storing operands for the processors, an instruction unit for specifying address offsets and operations to be performed by the processors, and an invariant address unit for combining the address offsets with a modifiable pointer to form source and destination addresses in the multiconnect unit. The instruction unit enables different ones of the processors as a function of which iteration of the loop is being executed, for example by means of processor control circuitry or by selectively providing instructions to the processors, so that different operations are performed during different iterations.