Patents by Inventor Ross Addinall

Ross Addinall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7541674
    Abstract: An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent pad or pads is at least the minimum required for wire bond assembly. For wire bond assembly a passivation layer exposing all pads is provided, whereas for flip-chip assembly a passivation layer exposes only certain pads so that conductive bumps may be provided. The provision of pads complying with the minimum spacing requirements for both flip-chip and wire bond assembly enables a “dual purpose” (e.g. one set of pads being for normal production and another set for testing purposes) die to be produced without any increase in die size.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: June 2, 2009
    Assignee: Agere Systems Inc.
    Inventors: Ross Addinall, Gareth Rhys Davies
  • Patent number: 6972494
    Abstract: An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent pad or pads is at least the minimum required for wire bond assembly. For wire bond assembly a passivation layer exposing all pads is provided, whereas for flip-chip assembly a passivation layer exposes only certain pads so that conductive bumps may be provided. The provision of pads complying with the minimum spacing requirements for both flip-chip and wire bond assembly enables a “dual purpose” (e.g. one set of pads being for normal production and another set for testing purposes) die to be produced without any increase in die size.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: December 6, 2005
    Assignee: Agere Systems Inc.
    Inventors: Ross Addinall, Gareth Rhys Davies
  • Publication number: 20050242431
    Abstract: An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent pad or pads is at least the minimum required for wire bond assembly. For wire bond assembly a passivation layer exposing all pads is provided, whereas for flip-chip assembly a passivation layer exposes only certain pads so that conductive bumps may be provided. The provision of pads complying with the minimum spacing requirements for both flip-chip and wire bond assembly enables a “dual purpose” (e.g. one set of pads being for normal production and another set for testing purposes) die to be produced without any increase in die size.
    Type: Application
    Filed: June 22, 2005
    Publication date: November 3, 2005
    Inventors: Ross Addinall, Gareth Davies
  • Patent number: 5568345
    Abstract: An overvoltage protection circuit employs a series of semiconductor switching elements, each element having a control terminal and two main conduction terminals, in a totem pole configuration and two potential dividers whose tapping points feed, respectively, the control terminals and the main terminal junctions of the switching elements. Both the series of switching elements and the two potential dividers are connected between a reference node (zero volts) and a node to be protected from an electrostatic discharge. The resistive elements of the potential dividers are so arranged that, in the absence of a static discharge, all switching elements are cut off and experience a substantially equal voltage across the respective main terminals. In this way, the circuit may be usefully employed in integrated circuits which are based on a low-voltage integration process but which have also a high-voltage-supply rail (e.g. 30 V). The switching elements may be bipolar transistors, and preferably Darlington pairs.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: October 22, 1996
    Assignee: Plessey Semiconductors Limited
    Inventors: Mark S. J. Mudd, Ross Addinall