Abstract: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

Abstract: A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state.

Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.

Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.

Abstract: The specification describes a CMOS compatible technique for programming MOS ROM devices. The technique involves doping the polysilicon gates of selected ROM devices with impurities having a type complementary to the channel, thereby raising the threshold voltage of those selected devices to a value above the operating voltage of the memory array. The programming step can be performed at the same time the CMOS gates are complementary doped thus allowing the ROM array to be programmed without additional processing steps.

Abstract: The specification describes a CMOS compatible technique for programming MOS ROM devices. The technique involves doping the polysilicon gates of selected ROM devices with impurities having a type complementary to the channel, thereby raising the threshold voltage of those selected devices to a value above the operating voltage of the memory array. The programming step can be performed at the same time the CMOS gates are complementary doped thus allowing the ROM array to be programmed without additional processing steps.

Abstract: An improved sense amplifier for accessing data stored in a flash memory or other memory, wherein the improvement consists of adding a variable impedance switch transistor to a conventional sense amplifier having a fixed impedance. The switch transistor has a low impedance for fast settling of charge during the pre-charge state of the flash memory, and has a high impedance during the sensing state of the flash memory for achieving a high gain and thus faster access of stored data than conventional sense amplifiers. The present invention also provides for better matching of sense amplifier transistors, thereby decreasing variations in performance between different transistors.

Abstract: A technique for improving the manufacturing yield of data processing memory. A memory array contains a known pattern of single-bit defects. Specifically, a first group of the memory cells contain flawless storage devices which are capable of being set to either of two possible stable states, i.e., a binary "1" or a binary "0." A second group of the memory cells contain the single-bit defects. These storage devices of the second group are capable of being set to only one of the two possible stable states. Before data is loaded into the memory, a coder codes the data such that bits to be loaded into the memory cells with bit defects match the state of the bit defect. The coder also generates code bits capable of decoding the coded data. A memory input-output circuit loads the code bits and the coded data blocks into the memory cells. When the memory input-output circuit accesses the memory, it passes the coded data blocks and the code bits to a decoder which uses the code bits to decode the data blocks.