Abstract: A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a number of steps in the code emitted by the binary translator.

Abstract: A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a minimal number of steps in the code emitted by the binary translator.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention process a virtual call during execution of a multi-threaded program by ensuring that the steps of patching the virtual call to the appropriate method are performed within a single instruction cycle. This prevents other threads from executing instructions related to the virtual call in the middle of the patching procedure. Methods, systems, and articles of manufacture consistent with the present invention identify a target, such as a targeted method and a class of a receiver object, associated with the virtual call and then determine an address identifier, such as a memory address pointer to the class of the receiver object.