Patents by Inventor Ross Cunniff
Ross Cunniff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9832388Abstract: Systems and methods for generating high dynamic images from interleaved Bayer array data with high spatial resolution and reduced sampling artifacts. Bayer array data are demosaiced into components of the YUV color space before deinterleaving. The Y component and the UV components can be derived from the Bayer array data through demosiac convolution processes. A respective convolution is performed between a convolution kernel and a set of adjacent pixels of the Bayer array that are in the same color channel. A convolution kernel is selected based the mosaic pattern of the Bayer array and the color channels of the set of adjacent pixels. The Y data and UV data are deinterleaved and interpolated into frames of short exposure and long exposures in the second color space. The short exposure and long exposure frames are then blended and converted back to a RGB frame representing a high dynamic range image.Type: GrantFiled: August 4, 2014Date of Patent: November 28, 2017Assignee: Nvidia CorporationInventors: Ricardo Motta, Brian Cabral, Sean Pieper, Ross Cunniff
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Publication number: 20160037044Abstract: Systems and methods for generating high dynamic images from interleaved Bayer array data with high spatial resolution and reduced sampling artifacts. Bayer array data are demosaiced into components of the YUV color space before deinterleaving. The Y component and the UV components can be derived from the Bayer array data through demosiac convolution processes. A respective convolution is performed between a convolution kernel and a set of adjacent pixels of the Bayer array that are in the same color channel. A convolution kernel is selected based the mosaic pattern of the Bayer array and the color channels of the set of adjacent pixels. The Y data and UV data are deinterleaved and interpolated into frames of short exposure and long exposures in the second color space. The short exposure and long exposure frames are then blended and converted back to a RGB frame representing a high dynamic range image.Type: ApplicationFiled: August 4, 2014Publication date: February 4, 2016Inventors: Ricardo MOTTA, Brian CABRAL, Sean PIEPER, Ross CUNNIFF
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Patent number: 8866833Abstract: A system, method, and computer program product are provided for a dynamic display refresh. In use, a state of a display device is identified in which an entirety of an image frame is currently displayed by the display device. In response to the identification of the state, it is determined whether an entirety of a next image frame to be displayed has been rendered to memory. The next image frame is transmitted to the display device for display thereof, when it is determined that the entirety of the next image frame to be displayed has been rendered to the memory. Further, a refresh of the display device is delayed, when it is determined that the entirety of the next image frame to be displayed has not been rendered to the memory.Type: GrantFiled: September 11, 2013Date of Patent: October 21, 2014Assignee: NVIDIA CorporationInventors: Tom Petersen, David Wyatt, Paul van der Kouwe, Emmett M. Kilgariff, Laurence Harrison, Jensen Huang, Tony Tamasi, Gerrit A. Slavenburg, Thomas F. Fox, David Matthew Stears, Robert Jan Schutten, Ross Cunniff, Ajay Kamalvanshi, Robert Osborne, Rouslan Dimitrov
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Publication number: 20140092113Abstract: A system, method, and computer program product are provided for a dynamic display refresh. In use, a state of a display device is identified in which an entirety of an image frame is currently displayed by the display device. In response to the identification of the state, it is determined whether an entirety of a next image frame to be displayed has been rendered to memory. The next image frame is transmitted to the display device for display thereof, when it is determined that the entirety of the next image frame to be displayed has been rendered to the memory. Further, a refresh of the display device is delayed, when it is determined that the entirety of the next image frame to be displayed has not been rendered to the memory.Type: ApplicationFiled: September 11, 2013Publication date: April 3, 2014Applicant: NVIDIA CorporationInventors: Tom Petersen, David Wyatt, Paul van der Kouwe, Emmett M. Kilgariff, Laurence Harrison, Jensen Huang, Tony Tamasi, Gerrit A. Slavenburg, Thomas F. Fox, David Matthew Stears, Robert Jan Schutten, Ross Cunniff, Ajay Kamalvanshi, Robert Osborne, Rouslan L. Dimitrov
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Patent number: 8564616Abstract: One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.Type: GrantFiled: July 17, 2009Date of Patent: October 22, 2013Assignee: Nvidia CorporationInventors: Ziyad S. Hakura, John Erik Lindholm, Emmett M. Kilgariff, Robert Ohannessian, Scott R. Whitman, James C. Bowman, Patrick R. Brown, Ross A. Cunniff
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Patent number: 8542247Abstract: One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.Type: GrantFiled: July 17, 2009Date of Patent: September 24, 2013Assignee: Nvidia CorporationInventors: Ziyad S. Hakura, John Erik Lindholm, Emmett M. Kilgariff, Robert Ohannessian, Scott R. Whitman, James C. Bowman, Patrick R. Brown, Ross A. Cunniff
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Patent number: 8253749Abstract: One embodiment of the present invention sets forth a set of application programming interface (API) extensions that enable a software application to control the processing work assigned to each GPU in a multi-GPU system. The software application enumerates a list of available GPUs, sets an affinity mask from the enumerated list of GPUs and generates an affinity device context associated with the affinity mask. The software application can then generate and utilize an affinity rendering context that directs rendering commands to a set of explicitly selected GPUs, thus allocating work among specifically selected GPUs. The software application is empowered to use domain specific knowledge to better optimize the work assigned to each GPU, thus achieving greater overall processing efficiency relative to the prior art techniques.Type: GrantFiled: March 7, 2007Date of Patent: August 28, 2012Assignee: NVIDIA CorporationInventors: Barthold B. Lichtenbelt, Jeffrey F. Juliano, Jeffrey A. Bolz, Ross A. Cunniff
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Patent number: 7969444Abstract: A method and apparatus for distributing the workload of rendering an image where texture mapping is involved among multiple graphics processing units (GPUs) are provided. The method generally entails dividing a texture map among multiple GPUs, performing texture mapping in each GPU to render image data in each GPU's frame buffer, combining the image data from each frame buffer, and scanning out the combined image to a display.Type: GrantFiled: December 12, 2006Date of Patent: June 28, 2011Assignee: NVIDIA CorporationInventors: Ralf Biermann, Barthold B. Lichtenbelt, Ross A. Cunniff, Jeffrey F. Juliano, Jeffrey A. Bolz
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Patent number: 7898549Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.Type: GrantFiled: December 12, 2007Date of Patent: March 1, 2011Assignee: NVIDIA CorporationInventors: Ross A. Cunniff, Matthew J. Craighead
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Patent number: 7623730Abstract: A texture mapping system comprises memory and a texture map manager. The memory stores a parametric texture map, and the parametric texture map has a plurality of texels. Each of the texels defines a variable expression that defines a luminosity parameter as a function of light direction. The texture map manager is configured to perform a rotation of a texture defined by the parametric texture map, and the texture map manager is further configured to adjust the variable expression of at least one of the texels to compensate for the rotation.Type: GrantFiled: July 30, 2003Date of Patent: November 24, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Bradford A. Ritter, Ross Cunniff
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Patent number: 7528839Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.Type: GrantFiled: August 13, 2003Date of Patent: May 5, 2009Assignee: Nvidia CorporationInventors: Ross A. Cunniff, Matthew J. Craighead
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Patent number: 7425956Abstract: One embodiment of the present invention sets forth a method for implementing occlusion testing prior to processing a primitive command. The method includes the steps of determining that an occlusion test should be performed on an enclosed primitive, saving the primitive command on a deferred list, and disabling a rendering functionality in hardware. The method also includes the step of performing an occlusion query on the enclosed primitive where a pixel count is generated that indicates how many pixels within a bounding volume defined around the enclosed primitive are visible. One advantage of this method is that it provides occlusion testing functionality for graphics applications that do not use the occlusion testing functionality provided by graphics APIs. Implementing occlusion testing functionality in this fashion reduces rendering time, thereby increasing rendering performance.Type: GrantFiled: June 21, 2005Date of Patent: September 16, 2008Assignee: NVIDIA CorporationInventors: Kevin T. Lefebvre, Ross A. Cunniff
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Publication number: 20050024374Abstract: A texture mapping system comprises memory and a texture map manager. The memory stores a parametric texture map, and the parametric texture map has a plurality of texels. Each of the texels defines a variable expression that defines a luminosity parameter as a function of light direction. The texture map manager is configured to perform a rotation of a texture defined by the parametric texture map, and the texture map manager is further configured to adjust the variable expression of at least one of the texels to compensate for the rotation.Type: ApplicationFiled: July 30, 2003Publication date: February 3, 2005Inventors: Bradford Ritter, Ross Cunniff
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Patent number: 6727899Abstract: A graphical display system of the present invention efficiently performs occlusion culling based on frame-to-frame temporal coherency. The graphical display system utilizes a frame buffer and rendering logic. The rendering logic is configured to receive graphical objects that define an image frame. In response to receiving one of the objects, the rendering logic is configured to make a determination as to whether the one object is visible in a previous image frame that was previously rendered to the frame buffer. The rendering logic is further configured to render the one object to the frame buffer based on the determination.Type: GrantFiled: July 10, 2001Date of Patent: April 27, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Don B. Hoffman, Joseph Norman Gee, Ross Cunniff, Howard D Stroyan
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Patent number: 6518968Abstract: The present invention provides a method and apparatus for performing H-space bump mapping. The apparatus of the present invention is a fragment processor of a computer graphics display system. The method of the present invention is performed by the fragment processor. In accordance with the method of the present invention, for each vertex of each polygon being processed, the fragment processor calculates both diffuse and specular lighting terms. Then, for each fragment within the polygon defined by the vertices, the fragment processor interpolates the specular and diffuse lighting terms to obtain diffuse and specular lighting terms for each fragment. If bump mapping has been enabled, the fragment processor adds perturbations to the diffuse and specular lighting terms to generate the bump mapping. Preferably, prior to performing the H-space bump mapping algorithm, texture coordinate gradient vectors are calculated for the image to be rendered.Type: GrantFiled: May 17, 2000Date of Patent: February 11, 2003Assignee: Hewlett-Packard CompanyInventors: Bradford A. Ritter, Ross Cunniff
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Patent number: 6476806Abstract: A method and apparatus is provided for performing occlusion testing in a computer graphics display system. The apparatus comprises logic configured to determine whether or not an object of a current image frame was occluded in a previous image frame. If a determination is made that the object was not occluded in the previous image frame, then the logic causes the object of the current image frame to be rendered to a frame buffer of the computer graphics display system. The current and previous image frames are each comprised of a plurality of objects, and the logic determines whether or not each of the objects of the current image frame were occluded in the previous image frame. The logic causes any objects of the current image frame that were not occluded in the previous image frame to be rendered to the frame buffer.Type: GrantFiled: April 16, 1999Date of Patent: November 5, 2002Assignee: Hewlett-Packard CompanyInventors: Ross Cunniff, Howard D. Stroyan, Norman Gee
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Publication number: 20020135587Abstract: The present invention is generally directed to a system and method for performing accumulation buffer operations using texture mapping hardware. In accordance with one aspect of the invention, a method is provided that operates by allocating a texture map of equal size as a display screen and copying contents of a frame buffer to the allocated texture map. The method then identifies an accumulation buffer operation and performs the accumulation buffer operation in a fragment unit. Preferably, the fragment unit includes an arithmetic logic unit (ALU) to perform high-speed mathematical operations. Finally, the method directs results of the accumulation buffer operation to the frame buffer, and copies contents of the frame buffer to the allocated texture map.Type: ApplicationFiled: March 18, 2002Publication date: September 26, 2002Inventor: Ross Cunniff
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Patent number: 6396502Abstract: The present invention is generally directed to a system and method for performing accumulation buffer operations using texture mapping hardware. In accordance with one aspect of the invention, a method is provided that operates by allocating a texture map of equal size as a display screen and copying contents of a frame buffer to the allocated texture map. The method then identifies an accumulation buffer operation and performs the accumulation buffer operation in a fragment unit. Preferably, the fragment unit includes an arithmetic logic unit (ALU) to perform high-speed mathematical operations. Finally, the method directs results of the accumulation buffer operation to the frame buffer, and copies contents of the frame buffer to the allocated texture map.Type: GrantFiled: October 15, 1999Date of Patent: May 28, 2002Assignee: Hewlett-Packard CompanyInventor: Ross Cunniff
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Publication number: 20010043216Abstract: A graphical display system of the present invention efficiently performs occlusion culling based on frame-to-frame temporal coherency. The graphical display system utilizes a frame buffer and rendering logic. The rendering logic is configured to receive graphical objects that define an image frame. In response to receiving one of the objects, the rendering logic is configured to make a determination as to whether the one object is visible in a previous image frame that was previously rendered to the frame buffer. The rendering logic is further configured to render the one object to the frame buffer based on the determination.Type: ApplicationFiled: July 10, 2001Publication date: November 22, 2001Inventors: Don B. Hoffman, Joseph Norman Gee, Ross Cunniff, Howard D. Stroyan
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Patent number: 5945992Abstract: In a client-server system in which scenes of objects are displayed by a client which receives data from a server, the rendering of the scene is speeded up by eliminating large amounts of data associated with objects which will not be rendered. This is accomplished by storing the object data in a tree hierarchy, and then first pruning those objects which are outside of the view of the observer in several defined steps. After the objects which will not be rendered have been pruned by the server, the data associated with objects which could not be pruned is transferred to the client over a data path, and the client goes through a number of steps to cull objects which will not be viewed. By utilizing the present invention, the display of graphics objects is significantly enhanced without need to use the former brute force methodology.Type: GrantFiled: May 29, 1996Date of Patent: August 31, 1999Assignee: Hewlett Packard CompanyInventor: Ross Cunniff