Patents by Inventor Ross E. Dermott
Ross E. Dermott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8400868Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: GrantFiled: July 18, 2011Date of Patent: March 19, 2013Assignee: Round Rock Research, LLCInventors: Aaron Schoenfeld, Ross E. Dermott
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Publication number: 20110273938Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: ApplicationFiled: July 18, 2011Publication date: November 10, 2011Applicant: ROUND ROCK RESEARCH, LLCInventors: Aaron M. Schoenfeld, Ross E. Dermott
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Patent number: 7983110Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: GrantFiled: September 28, 2009Date of Patent: July 19, 2011Assignee: Round Rock Research, LLCInventors: Aaron M. Schoenfeld, Ross E. Dermott
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Publication number: 20100014371Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Inventors: Aaron M. Schoenfeld, Ross E. Dermott
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Patent number: 7606101Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: GrantFiled: August 17, 2006Date of Patent: October 20, 2009Assignee: Micron Technology, Inc.Inventors: Aaron M. Schoenfeld, Ross E. Dermott
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Patent number: 7106646Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: GrantFiled: July 18, 2005Date of Patent: September 12, 2006Assignee: Micron Technology, Inc.Inventors: Aaron M. Schoenfeld, Ross E. Dermott
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Patent number: 7076012Abstract: A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The pulse generator is configured to receive a delay clock signal generated based on the input clock signal and generate a pulse, the pulse having a falling edge corresponding to a rising edge of the delay clock signal. The measure delay array is coupled to the pulse generator to receive the pulse. The measure circuit is configured to determine a position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal. The forward delay array is configured to receive the input clock signal and delay the input clock signal based on the position determined by the measure circuit to generate the output clock signal. A method for synchronizing an output clock signal with an input clock signal includes receiving a delay clock signal generated based on the input clock signal.Type: GrantFiled: August 29, 2002Date of Patent: July 11, 2006Assignee: Micron Technology, Inc.Inventors: Ross E. Dermott, Tyler J. Gomm
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Patent number: 6975556Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.Type: GrantFiled: October 9, 2003Date of Patent: December 13, 2005Assignee: Micron Technology, Inc.Inventors: Aaron M. Schoenfeld, Ross E. Dermott
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Patent number: 6781861Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.Type: GrantFiled: April 28, 2003Date of Patent: August 24, 2004Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
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Patent number: 6737897Abstract: A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.Type: GrantFiled: August 29, 2002Date of Patent: May 18, 2004Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Travis E. Dirkes, Ross E. Dermott, Daniel R. Loughmiller, Scott E. Smith
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Patent number: 6728163Abstract: A method and apparatus is provided for performing a filter control of a delay lock loop circuit. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A synchronized output signal is generated based upon the coarse delay and the fine delay. The apparatus of the present invention includes a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter to provide a filter response to the phase difference. The filter response is capable of providing a coarse delay and/or a fine delay.Type: GrantFiled: August 23, 2002Date of Patent: April 27, 2004Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Ross E. Dermott
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Publication number: 20040044918Abstract: A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The pulse generator is configured to receive a delay clock signal generated based on the input clock signal and generate a pulse, the pulse having a falling edge corresponding to a rising edge of the delay clock signal. The measure delay array is coupled to the pulse generator to receive the pulse. The measure circuit is configured to determine a position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal. The forward delay array is configured to receive the input clock signal and delay the input clock signal based on the position determined by the measure circuit to generate the output clock signal. A method for synchronizing an output clock signal with an input clock signal includes receiving a delay clock signal generated based on the input clock signal.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventors: Ross E. Dermott, Tyler J. Gomm
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Publication number: 20040037159Abstract: A method and apparatus is provided for performing a filter control of a delay lock loop circuit. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A synchronized output signal is generated based upon the coarse delay and the fine delay. The apparatus of the present invention includes a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter to provide a filter response to the phase difference. The filter response is capable of providing a coarse delay and/or a fine delay.Type: ApplicationFiled: August 23, 2002Publication date: February 26, 2004Inventors: Tyler J. Gomm, Ross E. Dermott
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Publication number: 20030189866Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.Type: ApplicationFiled: April 28, 2003Publication date: October 9, 2003Inventors: Tyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
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Patent number: 6586979Abstract: A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.Type: GrantFiled: March 23, 2001Date of Patent: July 1, 2003Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Travis E. Dirkes, Ross E. Dermott, Daniel R. Loughmiller, Scott E. Smith
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Patent number: 6556489Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.Type: GrantFiled: August 6, 2001Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
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Publication number: 20030026137Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.Type: ApplicationFiled: August 6, 2001Publication date: February 6, 2003Inventors: Tyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
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Publication number: 20020190767Abstract: A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.Type: ApplicationFiled: August 29, 2002Publication date: December 19, 2002Applicant: Micron Technology, Inc.Inventors: Tyler J. Gomm, Travis E. Dirkes, Ross E. Dermott, Daniel R. Loughmiller, Scott E. Smith
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Publication number: 20020135409Abstract: A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.Type: ApplicationFiled: March 23, 2001Publication date: September 26, 2002Applicant: Micron Technology, Inc.Inventors: Tyler J. Gomm, Travis E. Dirkes, Ross E. Dermott, Daniel R. Loughmiller, Scott E. Smith