Patents by Inventor Ross E. Noble

Ross E. Noble has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8247850
    Abstract: A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: August 21, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dharmesh Jawarani, Ross E. Noble, David C. Wang
  • Patent number: 8039386
    Abstract: A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: October 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thuy B. Dao, Ross E. Noble, Dina H. Triyoso
  • Publication number: 20110237073
    Abstract: A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 29, 2011
    Inventors: Thuy B. Dao, Ross E. Noble, Dina H. Triyoso
  • Patent number: 7972922
    Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: July 5, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hunter J. Martinez, John J. Hackenberg, Jill Hildreth, Ross E. Noble
  • Publication number: 20100129952
    Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Inventors: Hunter J. Martinez, John J. Hackenberg, Jill Hildreth, Ross E. Noble
  • Patent number: 7611936
    Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: November 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Ross E. Noble, Raghaw S. Rai
  • Publication number: 20080280429
    Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Inventors: Leo Mathew, Ross E. Noble, Raghaw S. Rai
  • Publication number: 20080164531
    Abstract: A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Inventors: Dharmesh Jawarani, Ross E. Noble, David C. Wang
  • Patent number: 6908822
    Abstract: An insulating layer (24, 66, 82) is formed over a stack (14) of materials and a semiconductor substrate (12) and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers (26) are formed over the insulating layer (24), the insulating layer (24) is etched, and heavily doped regions (36) are formed adjacent the spacers. The spacers (26) are then removed and extension regions (50) and optional halo regions (46) are formed by implanting through the insulating layer (24). In one embodiment, the insulating layer (24) is in contact with the semiconductor substrate (12). In one embodiment, the stack (14) is a gate stack including a gate dielectric (18), a gate electrode (16), and an optional capping layer (22). The insulating layer (24, 66, 82) may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer (24, 66, 82) may be hafnium oxide.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: June 21, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael J. Rendon, John M. Grant, Ross E. Noble