Abstract: A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads.

Abstract: A sorting algorithm is applied to an array data structure to arrange array elements according to the predicted frequency by which those array elements are likely to be modified. Higher modification frequency array elements are arranged proximate the end of the array to minimize the number of array elements that will typically need to be updated in response to modification of these array elements, reserving the modifications that require more array elements to be updated to those array elements that have a lower likelihood of modification. A sorting algorithm suitable for use in memory compression arranges blocks for a given page in reverse order since data located proximate the beginning of a page has a higher probability of being modified than the data proximate the end of the page.

Abstract: Logic for decreasing the number of cache lines dedicated to user data. When pools for allocation are selected using a dynamic storage allocation procedure, the size of a data block is compared to the size of the allocated pool. If the comparison results meet a predetermined criterion, the logic aligns the data to the beginning of a cache line and places the header in a separate cache line that may be deallocated. And if the data will fit within one-half of a cache slot in the allocated pool, then the line or lines having the header data can be re-used as the header is deallocated. Otherwise, user data blocks are placed in cache lines that are spatially local.