Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a substrate in direct mechanical contact with a conductive element thereon. An opening in the EDL exposes the conductive element and create a microvia in the EDL. A sidewall and bottom wall surface of the microvia are treated to promote adhesion of copper and are plated with a layer of copper that includes a copper layer on a copper seed layer and is in direct mechanical and electrical contact with the conductive element. A wet solder paste is deposited on the layer of copper to overfill a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect. A stiffener is attached to the EDL using a first adhesive.

Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.

Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.