Abstract: A manufacturing process for a structure having a porcelain body and a flange includes: inserting an end portion of the body into a flange opening, providing a gap between the body end portion and a metal surface of the flange, filling the gap with adhesive to create a bond between the surfaces, installing an electrically active subassembly in the porcelain body and placing the structure in a heated environment to simultaneously dry the subassembly and fully cure the adhesive to provide the bond.

Abstract: A manufacturing process for a structure having a porcelain body and a flange includes: inserting an end portion of the body into a flange opening, providing a gap between the body end portion and a metal surface of the flange, filling the gap with adhesive to create a bond between the surfaces, installing an electrically active subassembly in the porcelain body and placing the structure in a heated environment to simultaneously dry the subassembly and fully cure the adhesive to provide the bond.

Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.

Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.

Abstract: This document describes systems and methods for providing an automatic gain control transimpedance interface apparatus for a photodiode. In one example, the interface apparatus includes a cascade of at least one gain stage. A voltage signal is fed back from a noninverting output of the at least one cascaded gain stage to a preceding noninverting input of the at least one cascaded gain stage. Another voltage signal is fed back from an inverting output of the at least one cascaded gain stage to a preceding inverting input of the at least one cascaded gain stage. The feedback configuration is believed to reduce peaking and/or pole shifting as the AGC varies the gain of the at least one gain stage. The AGC improves dynamic range utilization. One example provides a gain stage with a single pole frequency response and omits emitter-follower buffers between gain stages that produce hidden poles.