Patents by Inventor Ross Sinclair Scouller

Ross Sinclair Scouller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device configurable as interleaved or non-interleaved memory
    Patent number: 8327092
    Abstract: A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evandro José Pitaro Borracini, Marcelo Del Fiore de Araujo, Jefferson Bastreghi, Ross Sinclair Scouller
  • MEMORY DEVICE AND METHOD
    Publication number: 20110072190
    Abstract: A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Evandro José Pitaro Borracini, Marcelo Del Fiore de Araujo, Jefferson Bastreghi, Ross Sinclair Scouller