Abstract: In an embodiment, an adapter assembly includes a plurality of system connectors configured to simultaneously engage a plurality of receiving connectors of an external system when inserted in the external system and simultaneously disengage from the plurality of receiving connectors of the external system when disengaged from the external system. The adapter assembly includes a device-receiving connector configured to engage a connector of a removable device, where the adapter assembly is configured to house at least a portion of the removable device. The adapter assembly includes connections between at least a portion of the plurality of system connectors and the device-receiving connector, where the connections are configured to route communication lanes of the removable device to one or more of the plurality of system connectors.

Abstract: A storage system using dual error detection and repair (“EDR”) using a host memory buffer (“HMB”) is disclosed. In one aspect, the EDR can be CRC or ECC. The storage system is able to retrieve information from an SSD and reformatting the information into a data structure based on a host based a random-access memory (“RAM”) storage configuration. After designating a portion of RAM word for storing data and another portion of RAM word for storing data EDR, the data is organized according to the RAM word configuration with EDR. Upon generating transmission EDR according to a packet structure capable of carrying data for transmission, the system is configured to discard transmission EDR and stores the data with data EDR in the RAM inside of the host upon arrival from the SSD via a bus.

Abstract: A non-volatile memory (“NVM”) solid state drive (“SSD”) auxiliary (“NSA”) plug, capable of providing bridge function and memory storage, is structured in a small form-factor pluggable (“SFP”) or quad small form-factor pluggable (“QSFP”) configuration. In one aspect, an SFP auxiliary plug (“SAP”) or NSA plug includes an Ethernet connector, NVM storage, bridge component, and memory controller. The Ethernet connector is pluggable to an Ethernet socket situated at a network system for data transmission. The NVM storage can store information persistently. The bridge component facilitates protocol conversion capable of converting data formatted between Ethernet protocol and a serial bus protocol for network communication. The memory controller is able to route data traffic between an output port of NSA plug and the NVM storage.

Abstract: A method or system capable of providing additional storage capacity using small form-factor (“SFP”) non-volatile memory (“NVM”) solid state drive (“SSD”) with modular to modular configuration is disclosed. A system includes a processing device, SFP auxiliary plug (“SAP”), and power SAP. In one embodiment, the processing device includes multiple SFP sockets operable to provide data communication. The SAP, having a SSD connector and an auxiliary connector, facilitates storing information persistently via NVM. The SSD connector of SAP is used for communicating with the processing device when the SAP is plugged into one of the SFP sockets. The power SAP, having a power connector and a power extension connector, is capable of providing electrical power to the SAP when the power extension connector and the auxiliary connector are coupled or connected.

Abstract: A data storage device includes a device sleep state pin and device sleep state logic to allow the data storage device to store security keys and necessary device sleep state logic together in a volatile logical data storage element. The volatile logical data storage element may be on-chip or off-chip. Device sleep state logic parameters for powering down PHYs while in a device sleep state determine the power characteristics of the device sleep state.

Abstract: A data storage device includes a device sleep state pin and device sleep state logic to allow the data storage device to store security keys and necessary device sleep state logic together in a volatile logical data storage element. The volatile logical data storage element may be on-chip or off-chip. Device sleep state logic parameters for powering down PHYs while in a device sleep state determine the power characteristics of the device sleep state.

Abstract: Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge.

Abstract: Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge. Optionally, data stored on an SSD is hardened, such as in response to determining that the SSD is to be powered off. The hardening is via power supplied by an energy storage element, such as a super capacitor or a battery.

Abstract: An apparatus and an associated method of operation is provided for performing device communication in accordance with a standard protocol, while enabling deviation from the device communication without termination or corruption of the device communication. The apparatus incorporates a pair of state machines configured to provide standard protocol communication with interrupt capability. A first state machine functions to perform the communication process in accordance with the standard protocol. The first state machine is also configured to deviate from the communication process in order to perform another requested task. A second state machine functions to monitor the communication process being performed by the first state machine. Upon completion of the other requested task by the first state machine, a state of the communication process is provided by the second state machine to enable the communication process to be continued by the first state machine.

Abstract: Broadly speaking, an apparatus and associated method of operation is provided for controlling alignment signal transmission in an electronic communication process. More specifically, a programmable control is provided for controlling transmission of alignment signals in either a Serial Attached SCSI (SAS) or Serial ATA (SATA) communication process. The programmable control includes a counter operated to sequentially modify a count value. When the count value is equal to a programmed alignment trigger value, the programmable control is configured to generate and transmit an alignment signal through the initiator transceiver to the target transceiver. Thus, the apparatus and associated method of operation controls a rate at which alignment signals are transmitted in a SAS/SATA communication process.

Abstract: Broadly speaking, a method and apparatus is provided for identifying and responding to a deadlock condition in a SAS/SATA communication process. More specifically, an initiator device involved in the SAS/SATA communication process is defined to recognize a received error signal as an indication of a potential communication deadlock condition. The initiator device is further defined to promptly respond to the received error signal with a course of action for recovering from the communication deadlock condition.

Abstract: An apparatus for performing a boundary scan test is provided, along with method for integrating and operating the same. The apparatus includes an asynchronous flip-flop that has a data input, a data output, a system clock input, a set input, and a reset input. The apparatus also includes a test controller that has a test clock input, a first test data output, and a second test data output. The first test data output of the test controller is connected to the set input of the asynchronous flip-flop. In addition, the second test data output of the test controller is connected to the reset input of the asynchronous flip-flop. The test controller is configured to control the asynchronous flip-flop through the set input and the reset input. The apparatus for performing the boundary scan test avoids introduction of adverse delay and skew effects caused by multiplexing circuitry.

Abstract: Broadly speaking a method and an apparatus is disclosed for enabling vendor-specific communication between devices of a common vendor. More specifically, the present invention provides a method and an apparatus for using vendor-specific cyclic redundancy check (CRC) data to identify a communication as containing vendor-specific data. The method and apparatus of the present invention does not inhibit compatibility between the vendor device and another device operating in accordance with a standard communication protocol. Additionally, the method and apparatus of the present invention allows the devices of the common vendor to implement features and functionality that rely on efficient and protected vendor-specific communication.

Abstract: A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be maintained in transmit order. The wired endian format is defined to allow for interfacing with both a big endian format and a little endian format. Thus, a device operating in accordance with the wired endian format is able to interface with both a device operating in accordance with the big endian format (e.g., a Serial Attached SCSI (SAS) device) and a device operating in accordance with the little endian format (e.g., a Serial ATA (SATA) device). Furthermore, since the device operating in accordance with wired endian format implements circuitry compliant with the wired endian format, duplication of circuitry to define separate data paths for interfacing with the big endian and little endian formats, respectively, is avoided.

Abstract: An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal is then asserted at the reset pin, and a reset time is measured. The reset time is defined as the time period beginning when the reset signal is asserted and ending when the storage element resets. In this manner, the reset time can be used to determine a speed of the IC logic relative to a process. In one aspect, delay logic is provided that is in electrical communication with the reset pin and in electrical communication with the storage element. In this aspect, the delay logic delays the reset signal for a predetermined time period. Optionally, the reset time can be compared to a predetermined fast corner reset time and a predetermined slow corner reset time. Further, the IC logic speed can be correlated to a simulation using the embodiments of the present invention.

Abstract: Broadly speaking, a method and corresponding apparatus is provided for controlling a data output rate of an electronic device. More specifically, the method and corresponding apparatus enables an equivalent data output rate to be obtained from each of an ASIC and an FPGA prototype of the ASIC while maintaining equivalent logic between the ASIC and the FPGA prototype. A validity bit is attached to each output data signal in accordance with each cycle of a clock signal. The validity bit provides an indication as to whether the associated data signal should be processed (i.e., transmitted as output) normally. Only valid output data signals as identified by their validity bit value are transmitted. Thus, the validity bit values associated with successive data signals can be defined to generate a particular data output rate.