Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.

Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.

Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.

Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

Abstract: A system provides a mechanism for increasing reliability by allowing margins to be evaluated and if one or more margins of a current configuration are too small, system configuration is modified to increase the margin. A computing device determines through training a first operating point of at least one operational characteristic of the system and a first margin associated therewith. The first margin is compared to a predetermined threshold margin and if the first margin is less than the predetermined threshold margin, the configuration of the system is adjusted to provide a configuration with greater margin for the operational characteristic. The system is retrained with the new configuration to determine a second operating point and a second margin associated therewith and compares the second margin to the threshold margin to determine if the second margin is more than the threshold margin, to satisfy reliability requirements.

Abstract: A system provides a mechanism for increasing reliability by allowing margins to be evaluated and if one or more margins of a current configuration are too small, system configuration is modified to increase the margin. A computing device determines through training a first operating point of at least one operational characteristic of the system and a first margin associated therewith. The first margin is compared to a predetermined threshold margin and if the first margin is less than the predetermined threshold margin, the configuration of the system is adjusted to provide a configuration with greater margin for the operational characteristic. The system is retrained with the new configuration to determine a second operating point and a second margin associated therewith and compares the second margin to the threshold margin to determine if the second margin is more than the threshold margin, to satisfy reliability requirements.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A method of hot swapping memory is described. A memory system includes a plurality of memory banks such that a memory word is divided into the memory banks. The memory system is provided a spare memory bank. One of the memory banks is selected to be replaced. The memory system is configured to perform write operations associated with the selected memory bank to both the selected and spare memory banks. Atomic read and write operations are performed such that the content of the selected memory bank is copied to the spare memory bank. The memory system is subsequently configured to redirect operations to be performed on the selected memory bank to the spare memory bank such that the selected memory bank can be hot replaced.

Abstract: A host is coupled to a serially connected chain of memory modules. In one embodiment, a method for initializing the host and each of memory modules includes the host transmitting a first synchronization pattern and a second synchronization pattern downstream in response to a reset condition. The method also includes each memory module in the serially connected chain of memory modules receiving and forwarding the first and the second synchronization pattern. Each memory module receives and forwards the first and the second synchronization pattern. Further, the method includes the host transmitting a plurality of NOP packets downstream in response to transmitting the second synchronization pattern. Lastly, the method includes a portion of the memory modules injecting and transmitting NOP packets upstream in response to receiving the second synchronization pattern from downstream.

Abstract: An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, includes a bus configured to provide bus request routing; and a bus request route switching stage coupled to the bus and configured to select a first route configuration if two processors are coupled to the bus. The switching stage is also configured to select a second route configuration if more that two processors are coupled to the bus. The switching stage determines if two or more processors are coupled to the bus. A logic block may be used to determine the required configuration based on the detected processor population.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, includes a bus configured to provide bus request routing; and a bus request route switching stage coupled to the bus and configured to select a first route configuration if two processors are coupled to the bus. The switching stage is also configured to select a second route configuration if more that two processors are coupled to the bus. The switching stage determines if two or more processors are coupled to the bus. A logic block may be used to determine the required configuration based on the detected processor population.

Abstract: A method of hot swapping memory is described. A memory system includes a plurality of memory banks such that a memory word is divided into the memory banks. The memory system is provided a spare memory bank. One of the memory banks is selected to replace. The memory system is configured to perform write operations associated with the selected memory bank to both the selected and spare memory banks. Atomic read and write operations are performed such that the content of the selected memory bank is copied to the spare memory bank. The memory system is configured to redirect operations to be performed on the selected memory bank to the spare memory bank such that the selected memory bank can be hot replaced.

Abstract: A fast cache hit detection method and apparatus. The present invention provides a method and apparatus for quickly determining whether there is a cache hit in cache memory systems utilizing error corrected tags. The hit detection process is split into two paths. The first path includes a circuit to check and correct a tag stored in the cache memory. The second path tests the validity of the tag stored in the cache memory by computing the appropriate ECC information using memory address information supplied by the computer CPU and comparing the tag and ECC stored in the cache memory to the CPU address and computed ECC. As the computed ECC is performed in parallel with the cache RAM access, this second path provides hit confirmation faster than the first path which must process the tag and ECC stored in the cache RAM through a ECC check and correction circuit. If a fast hit is confirmed, then the cache memory system can proceed to supply cache data to the CPU.

Abstract: A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor and to the system memory. The first cache memory contains a subset of data in the system memory. A second cache memory is also connected to the processor. The second cache memory contains a subset of data in the first cache memory. Data integrity in the system memory is maintained using the first cache memory only. Whenever the processor writes data, the processor writes data both to the first cache memory and to the second cache memory. Whenever the processor reads data, the processor attempts to read data from the second cache memory. If there is a miss at the second cache memory, the processor attempts to read data from the first cache memory. If there is a miss at the first cache memory, the data is retrieved from the system memory and placed in the first cache memory.

Abstract: An improved integrated circuit chip design which is better adapted to testing using existing circuit testers is disclosed. The chip includes a parallel load instruction which reduces the number of words of tester memory needed to load the internal scan registers. The parallel load instruction loads memory cells connected to the input pins of the chip which are then shifted into the scan registers.