Patents by Inventor Rosy Zhao

Rosy Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942459
    Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
  • Publication number: 20230260975
    Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
  • Publication number: 20230102959
    Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hope Chiu, Hua Tan, Kent Yang, Weiting Jiang, Jerry Tang, Simon Dong, Yuequan Shi, Rosy Zhao