Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: A method of manufacturing a semiconductor structure includes a number of operations. A first oxide layer is provided on a semiconductor integrated circuit. A conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer. An etch stop layer is formed on the top surface of the first oxide layer. A second oxide layer is formed on the etch stop layer. A through via is formed extending through the second oxide layer and the etch stop layer to expose the conductive layer. Acid is provided on the conductive layer to form a protective layer on the conductive layer. The protective layer includes a compound of the acid and material of the conductive layer. A fence of the second oxide layer at an edge on the through via is removed at the through via by a hydrofluoric acid etching.

Abstract: The disclosure provides a semiconductor structure comprising a plurality of bit line structures and a method for manufacturing the same. In the present disclosure, by allowing at least one of the bit line structures to have a width at its top less than a width at its bottom, the semiconductor structure may have an increased total tungsten volume. The contact surface between the bit line structures and the landing pad is increased, so the landing pad resistance can be decreased. Therefore, the performance of the semiconductor structure can be enhanced.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.

Abstract: A method of manufacturing a semiconductor device is provided. A precursor structure is formed, in which the precursor structure includes a patterned substrate having at least one trench therein, an oxide layer covering the patterned substrate, and a nitride layer on the oxide layer and exposing a portion of the oxide layer in the trench. A first barrier layer and a first gate structure is formed on the oxide layer. A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer. A second barrier layer is formed on the first gate structure and the oxide layer. A portion of the second barrier layer is removed with the etchant. A second gate structure is formed on the second barrier layer.

Abstract: The present disclosure provides a semiconductor memory device and a method for manufacturing the semiconductor memory device. The method includes steps of: providing a substrate including a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer; forming a trench between the storage area and the peripheral area; filling the trench with a nitride material; forming a first oxide layer above the nitride material in the trench and on the landing pad; forming a nitride layer above the first oxide layer; and forming a second oxide layer above the nitride layer.

Abstract: A method of manufacturing a semiconductor device is provided. A precursor structure is formed, in which the precursor structure includes a patterned substrate having at least one trench therein, an oxide layer covering the patterned substrate, and a nitride layer on the oxide layer and exposing a portion of the oxide layer in the trench. A first barrier layer and a first gate structure is formed on the oxide layer. A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer. A second barrier layer is formed on the first gate structure and the oxide layer. A portion of the second barrier layer is removed with the etchant. A second gate structure is formed on the second barrier layer.

Abstract: A method of forming a semiconductor structure includes following steps. A substrate is formed. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. The dielectric stack is etched to form an opening such that the contact of the substrate is exposed. The opening has a bottom portion and a top portion communicated to the bottom portion. The dielectric stack is etched again to expand the bottom portion of the opening.