Abstract: An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. Transactions are performed between the master device and the slave device, where each transaction comprises or more transfers, and each transfer comprises a request and a response. A first connection path between the first interface and the second interface is provided that comprises a first plurality of pipeline stages. The first connection path forms a default path for propagation of the requests and responses of the transfers. A second connection path is also provided between the first interface and the second interface that comprises a second plurality of pipeline stages, where the second plurality is less than the first plurality. Path selection circuitry is then used to determine presence of a fast path condition.

Abstract: An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. Transactions are performed between the master device and the slave device, where each transaction comprises or more transfers, and each transfer comprises a request and a response. A first connection path between the first interface and the second interface is provided that comprises a first plurality of pipeline stages. The first connection path forms a default path for propagation of the requests and responses of the transfers. A second connection path is also provided between the first interface and the second interface that comprises a second plurality of pipeline stages, where the second plurality is less than the first plurality. Path selection circuitry is then used to determine presence of a fast path condition.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: An integrated circuit device (100) comprising a first plurality of components (102-112), a second plurality of buses (114-124, 140, 142) for transmitting transaction requests from said components (102-112) to a resource (138) shared by said components (102-112) and a third plurality of arbiters (132-136) arranged in at least two levels of arbitration. Each transaction request has attached priority value that is used by the arbiters to determine which of the components should be granted access to the resource (138).

Abstract: A device for generating a priority value of a processor in a multiprocessor apparatus, the device comprising a counter, an interface for receiving signals from an arbiter, wherein the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus. The counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The device is also adapted to send the modified value of the counter as a new priority value to the arbiter.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: An integrated circuit device (100) comprising a first plurality of components (102-112), a second plurality of buses (114-124, 140, 142) for transmitting transaction requests from said components (102-112) to a resource (138) shared by said components (102-112) and a third plurality of arbiters (132-136) arranged in at least two levels of arbitration. Each transaction request has attached priority value that is used by the arbiters to determine which of the components should be granted access to the resource (138).

Abstract: A method of initializing a booting procedure of a mobile platform having a certain NAND flash memory. The method comprises sending (304) an initial read command sequence to the NAND flash memory and detecting (305) if the NAND flash memory is responsive to the read command sequence. If the NAND flash memory is responsive to the read command sequence the mobile platform will be configured (306) to interface with the NAND flash memory. If the NAND flash memory is not responsive to the initial read command sequence, the method further comprises sending (307) another read command sequence to the NAND flash memory. The another read command sequence is associated with the initially sent read command sequence. Next, it is detected (308) if the NAND flash memory is responsive to the another read command sequence, and if so the mobile platform will be configured (309) to interface with the NAND flash memory.

Abstract: A device for generating a priority value of a processor in a multiprocessor apparatus, the device comprising a counter, an interface for receiving signals from an arbiter, wherein the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus. The counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The device is also adapted to send the modified value of the counter as a new priority value to the arbiter.

Abstract: The memory access capabilities of a host processor are used to facilitate the movement of instructions and data to an application-specific component having direct access to memory. Although the component executes code absent direct host processor control, the code may be uniquely tailored to the component's architecture. According to one embodiment, a flow of instructions requested by a host processor from a memory device is monitored. The flow of instructions is routed to an application-specific component in response to identifying code embedded in the flow of instructions targeted for execution by the component. While the instruction flow is routed to the component, a sequence of instructions is directed to the host processor that maintains instruction execution flow in the host processor, e.g., no-op instructions. When the end of the application-specific code is detected, the instruction flow is re-routed to the host processor for execution.

Abstract: According to one embodiment, an embedded system includes at least one processor, memory and peripheral subsystem. Each subsystem has a terminating node configured to issue and receive messages for the subsystem. A bus fabric interconnects the subsystems and includes a plurality of non-terminating nodes located at different points in the bus fabric and interconnected with the terminating nodes to form a peer-to-peer communication matrix between the subsystems. The non-terminating nodes route the messages over the peer-to-peer matrix so that instructions included in the messages are delivered to the terminating nodes identified in the messages for execution. Each node is assigned one or more unique object identifiers for identifying the nodes and the instructions included in the messages identify different control and data flow functions supported by different ones of the subsystems.

Abstract: A method of initializing a booting procedure of a mobile platform having a certain NAND flash memory. The method comprises sending (304) an initial read command sequence to the NAND flash memory and detecting (305) if the NAND flash memory is responsive to the read command sequence. If the NAND flash memory is responsive to the read command sequence the mobile platform will be configured (306) to interface with the NAND flash memory. If the NAND flash memory is not responsive to the initial read command sequence, the method further comprises sending (307) another read command sequence to the NAND flash memory. The another read command sequence is associated with the initially sent read command sequence. Next, it is detected (308) if the NAND flash memory is responsive to the another read command sequence, and if so the mobile platform will be configured (309) to interface with the NAND flash memory.

Abstract: The memory access capabilities of a host processor are used to facilitate the movement of instructions and data to an application-specific component having direct access to memory. Although the component executes code absent direct host processor control, the code may be uniquely tailored to the component's architecture. According to one embodiment, a flow of instructions requested by a host processor from a memory device is monitored. The flow of instructions is routed to an application-specific component in response to identifying code embedded in the flow of instructions targeted for execution by the component. While the instruction flow is routed to the component, a sequence of instructions is directed to the host processor that maintains instruction execution flow in the host processor, e.g., no-op instructions. When the end of the application-specific code is detected, the instruction flow is re-routed to the host processor for execution.

Abstract: A processing arrangement for a computer comprising: first processor means (1) for processing a first set of instructions; and second processor means (2) for processing a second set of instructions, the second set of instructions being a subset of the first set of instructions, wherein the second processor means (2) is arranged to receive control signals and to process instructions in dependence upon those control signals without reference to the first processor means.