Patents by Inventor Rowel S. Garcia

Rowel S. Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747439
    Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Rowel S. Garcia, Sanjeev N. Trika, Jawad B. Khan
  • Publication number: 20190102262
    Abstract: A storage controller performs continuous checkpointing. With continuous checkpointing, the information necessary for system rollback is continuously recorded without the need of a specific command. With the rollback information, the system can rollback or restore to any previous state up to a number of previous writes or up to an amount of data. The number of writes or the amount of data that can be restored are configurable.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Vadim SUKHOMLINOV, Kshitij A. DOSHI, Tamir D. MUNAFO, Sanjeev N. TRIKA, Urvi PATEL, Rowel S. GARCIA
  • Patent number: 10216415
    Abstract: Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Rowel S. Garcia, Sanjeev N. Trika
  • Publication number: 20190042111
    Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Rowel S. GARCIA, Sanjeev N. TRIKA, Jawad B. KHAN
  • Publication number: 20190042460
    Abstract: A computer system that includes a host based byte addressable persistent buffer to store a Logical to Physical (L2P) indirection table for a solid-state drive is provided. Shutdown and startup of the computer system is accelerated by storing the L2P indirection table in the host based byte addressable persistent buffer.
    Type: Application
    Filed: February 7, 2018
    Publication date: February 7, 2019
    Inventors: Sanjeev N. TRIKA, Rowel S. GARCIA
  • Patent number: 9996466
    Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Rowel S. Garcia
  • Publication number: 20170336981
    Abstract: Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: Rowel S. GARCIA, Sanjeev N. TRIKA
  • Publication number: 20170286294
    Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 5, 2017
    Inventors: Sanjeev N. Trika, Rowel S. Garcia
  • Patent number: 9652384
    Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Rowel S. Garcia
  • Publication number: 20160378352
    Abstract: Methods and apparatus related to efficient Solid State Drive (SSD) data compression scheme and layout are described. In one embodiment, logic, coupled to non-volatile memory, receives data (e.g., from a host) and compresses the data to generate compressed data prior to storage of the compressed data in the non-volatile memory. The compressed data includes a compressed version of the data, size of the compressed data, common meta information, and final meta information. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Jawad B. Khan, Richard P. Mangold, Vinodh Gopal, Rowel S. Garcia, Knut S. Grimsrud
  • Publication number: 20160170878
    Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Inventors: Sanjeev N. Trika, Rowel S. Garcia