Abstract: Single-transistor memory cell including a three-dimensional capacitor and methods for fabricating the cell are disclosed. The method includes steps for defining a source and drain, forming a channel between the source and drain, and forming a gate area of a transistor. The method also includes forming a first and second capacitor plate of a three-dimensional capacitor coupled to the drain of the transistor. In one respect, the first capacitor plate may be formed substantially simultaneously with the step of forming the channel. Additionally, the second capacitor plate may be formed substantially simultaneously with the step of defining the gate area of the transistor. The capacitor may include a three-dimensional fin capacitor and the transistor may include, for example, a multi-gate field effect transistor, a fin field effect transistor, a tri-gate transistor, a ? transistor, and a ? transistor.