Patents by Inventor Roy A. Carruthers
Roy A. Carruthers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8927057Abstract: A method for forming a single, few-layer, or multi-layer graphene and structure is described incorporating selecting a substrate having a buried layer of carbon underneath a metal layer, providing an ambient and providing a heat treatment to pass carbon through the metal layer to form a graphene layer on the metal layer surface or incorporating a metal-carbon layer which is heated to segregate carbon in the form of graphene to the surface or chemically reacting the metal in the metal-carbon layer with a substrate containing Si driving the carbon to the surface whereby graphene is formed.Type: GrantFiled: February 22, 2010Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Ageeth A. Bol, Roy A. Carruthers, Jack O. Chu, Alfred Grill, Christian Lavoie, Katherine L. Saenger, James C. Tsang
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Publication number: 20130049199Abstract: Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Paul R. Besser, Roy A. Carruthers, Christopher P. D'Emic, Christian Lavoie, Conal E. Murray, Kazuya Ohuchi, Christopher Scerbo, Bin Yang
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Publication number: 20130049200Abstract: Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to fond an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A silicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.Type: ApplicationFiled: August 30, 2012Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Paul R. Besser, Roy A. Carruthers, Christopher P. D'Emic, Christian Lavoie, Conal E. Murray, Kazuya Ohuchi, Christopher Scerbo, Bin Yang
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Patent number: 8154130Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: April 23, 2008Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
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Patent number: 8125082Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.Type: GrantFiled: May 15, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Jia Chen, Christopher Detavernier, James M. Harper, Christian Lavoie
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Patent number: 8119466Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.Type: GrantFiled: June 3, 2011Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christopher G. M. M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
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Publication number: 20110256675Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.Type: ApplicationFiled: June 3, 2011Publication date: October 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christophe G.M.M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
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Publication number: 20110206934Abstract: A method for forming a single, few-layer, or multi-layer graphene and structure is described incorporating selecting a substrate having a buried layer of carbon underneath a metal layer, providing an ambient and providing a heat treatment to pass carbon through the metal layer to form a graphene layer on the metal layer surface or incorporating a metal-carbon layer which is heated to segregate carbon in the form of graphene to the surface or chemically reacting the metal in the metal-carbon layer with a substrate containing Si driving the carbon to the surface whereby graphene is formed.Type: ApplicationFiled: February 22, 2010Publication date: August 25, 2011Applicant: International Business Machines CorporationInventors: Ageeth A. Bol, Roy A. Carruthers, Jack O. Chu, Alfred Grill, Christian Lavoie, Katherine L. Saenger, James C. Tsang
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Patent number: 8003453Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.Type: GrantFiled: May 22, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christopher G. M. M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
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Publication number: 20110162702Abstract: A method of texturing a surface of a substrate utilizing a phase-segregated mask and etching is disclosed. The resulting textured surface, which can be used as a component of a solar cell includes, in one embodiment, a randomly mixed collection of flat-topped and angled surfaces providing local high points and local low points. The flat-topped surfaces have an areal density of at least 1%, and the high points are coincident with the flat-topped surfaces. Moreover, a preponderance of said low points are approximately situated in a single common plane parallel to the plane defined by the flat-topped surfaces.Type: ApplicationFiled: January 6, 2010Publication date: July 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roy A. Carruthers, Keith E. Fogel, Daniel A. Inns, Katherine L. Saenger
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Patent number: 7784669Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: GrantFiled: August 5, 2009Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Kamalesh K. Srivastava, Sung K. Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey, Donald W. Henderson, David R. Di Milia, Richard P. Ferlita, Roy A. Carruthers
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Publication number: 20100155456Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: ApplicationFiled: August 5, 2009Publication date: June 24, 2010Applicant: International Business Machines Corp.Inventors: GARETH G. HOUGHAM, KAMALESH K. SRIVASTAVA, SUNG K. KANG, DA-YUAN SHIH, BRIAN R. SUNDLOF, S. JAY CHEY, DONALD W. HENDERSON, DAVID R. DI MILIA, RICHARD P. FERLITA, ROY A. CARRUTHERS
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Patent number: 7703661Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduced or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: GrantFiled: May 23, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Kamalesh K. Srivastava, Sung K. Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey, Donald W. Henderson, David R. Di Milia, Richard P. Ferlita, Roy A. Carruthers
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Patent number: 7682968Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: April 23, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
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Patent number: 7598516Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.Type: GrantFiled: January 7, 2005Date of Patent: October 6, 2009Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christophe G. M. M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
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Patent number: 7517795Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.Type: GrantFiled: October 20, 2006Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: Roy A. Carruthers, Cedrik Y. Cole, Christophe Detavernier, Christian Lavoie, Kenneth P. Rodbell
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Publication number: 20080299720Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.Type: ApplicationFiled: May 21, 2008Publication date: December 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roy A. Carruthers, Cedrik Y. Coia, Christophe Detavernier, Christian Lavoie, Kenneth P. Rodbell
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Publication number: 20080290142Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: ApplicationFiled: May 23, 2007Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gareth G. Hougham, Kamalesh K. Srivastava, Sung K. Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey, Donald W. Henderson, David R. Di Milia, Richard P. Ferlita, Roy A. Carruthers
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Patent number: 7449782Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: May 4, 2004Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
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Publication number: 20080246120Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.Type: ApplicationFiled: May 15, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy A. Carruthers, Jia Chen, Christophe Detavernier, James M. Harper, Christian Lavoie