Patents by Inventor Roy Badeau

Roy Badeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing verifier for MOS devices and related method
    Patent number: 6877142
    Abstract: The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: April 5, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nevine Nassif, Madhav Desai, James Arthur Farrell, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman
  • Timing verifier for MOS devices and related method
    Publication number: 20030149951
    Abstract: The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.
    Type: Application
    Filed: August 13, 2002
    Publication date: August 7, 2003
    Inventors: Nevine Nassif, Madhav Desai, James Arthur Farrell, Harry Ray Fair, Roy Badeau, Nicholas Lee Rethman
  • Timing verifier for MOS devices and related method
    Patent number: 6473888
    Abstract: The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: October 29, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Nevine Nassif, Madhav Desai, James Arthur Farrell, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman