Abstract: An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.

Abstract: The high speed greater than or equal to compare circuit comprises an equal to compare circuit having M number of exclusive-OR gates input into a NOR gate, each exclusive-OR gate N of the M number of exclusive-OR gates receiving as inputs a Nth bit of a first digital number having M bits and a corresponding Nth bit of a second digital number having M bits, wherein 1<N<M. Each exclusive-OR gate outputs a Nth not-equal signal indicating when the Nth bit of the first digital number is not equal to the corresponding Nth bit of the second digital number, whereby the output signal of the NOR gate indicates that the first digital number is equal to the second digital number.

Abstract: An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory.

Abstract: A BiCMOS output driver in which a bipolar device is driven by a control signal that biases the collector of an NFET. The control signal enables the bipolar to pull an output node to full potential (ground) quickly. The signal then falls within one nanosecond after the output reaches ground, pulling the bipolar out of saturation. A separate feedback device coupled between the base of the bipolar and ground can be added to pull the bipolar out of saturation before the control signal falls.

Abstract: A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor arranged in series with a second or pull-up P-channel transistor and a third P-channel transistor connected from the common point between the first and second transistors and the gate electrode of the first transistor. The first and second transistors are disposed between a data output terminal and a first voltage source having a supply voltage of a given magnitude, with the data output terminal also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor, disposed in a common N-well with the other P-channel transistors, is connected at its source to the first voltage source and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.

Abstract: A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches.

Abstract: A test circuit or system is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal voltages and currents and compared with the data written into the circuits or cells.

Abstract: This teaches a method of testing normally untestable, programmable integrated circuits before they are irreversibly programmed by providing the circuit with first and second impedances which combine to form an initial resultant impedance. The second of these impedances has a significantly higher level of impedance then does the first. The first of these impedances is required for testing purposes only and must be subsequently effectively removed from the circuit once testing of the circuit is completed. Once the circuit has been tested the second or higher impedance is made to interact with the circuit and functionally eliminate the first impedance from the circuit. The resultant impedance of the circuit after the first impedance has been functionally removed from the circuit can be either higher or lower than the pre-programmed initial resultant impedance of the circuit.