Abstract: Embodiments of the invention include a stacked device having a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region. The first epitaxial region comprising an asymmetric profile with a horizontal protrusion.

Abstract: A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.

Abstract: The present disclosure provides a graphene-based dispersion. Said dispersion is characterized by the presence of graphene at a concentration ranging from about 0.0001% (w/w) to about 20% (w/w). The present disclosure further provides a method of preparing the graphene-based dispersion comprising mixing components of the graphene-based dispersion in a high shear mixer. The graphene-based dispersion of the present disclosure is characterized by beneficial features such as but not limited to homogeneity and stability. Further provided in the present disclosure are applications of the graphene-based dispersion.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.

Abstract: Polymer fiber or corresponding fabric including graphene and/or its derivative(s), wherein the graphene including polymer fabric is characterized by feature selected from the group consisting of anti-microbial, antistatic, wicking, thermal cooling, anti-odour, and ultraviolet protection, or any combination thereof. The graphene including polymer fiber or fabric shows several further beneficial properties including but not limited to good/excellent washing fastness, rubbing fastness, perspiration fastness, sublimation fastness, and light fastness. A process by which the graphene and/or its derivative(s) is incorporated in a polymer during its synthesis. The polymer is subsequently drawn into a fiber or fabric, and is capable of being converted into commercial products. A method to improve the aforementioned properties in a polymer fiber or fabric.

Abstract: A method includes obtaining, by a processing device, data indicative of locations of defects of a substrate. The method further includes generating an image indicating the locations of the defects. The method further includes providing the image indicating the locations of the defects to a trained machine learning model. The method further includes obtaining, as output from the trained machine learning model, a classification of the locations of the defects. The method further includes performing a corrective action in view of the output from the trained machine learning model.

Abstract: Various embodiments of an apparatus, methods, systems and computer program products described herein are directed to an agricultural treatment system and method of operation. The agricultural treatment system may obtain imagery of emitted fluid projectiles at intended target locations. The system may identify positional parameters of a spraying head and/or motors used to maneuver the spraying head to emit the fluid projectile. The system may generate a calibration or lookup table based on a three-dimensional coordinate of the intended target location and of the positional parameters of the spraying head. The system may then use the lookup table to perform subsequent spray operations.

Abstract: Various embodiments of an apparatus, methods, systems and computer program products described herein are directed to an agricultural treatment system and method of operation. The agricultural treatment system may obtain with one or more image sensors at a first time period, a first set of images each comprising a plurality of pixels depicting a ground area and a first target agricultural object positioned in the ground area. The system may emit a first fluid projectile of a first fluid at the first target agricultural object. The system may obtain with the one or more image sensors at a second time period, a second set of images each comprising a plurality of pixels depicting the ground area and the agricultural object. The system may compare the first image with the second image to determine a change in pixels between at least a first image of the first set of images and at least a second image of the second set of images.

Abstract: A semiconductor device includes: a channel having layers of silicon separated from each other; a metal gate in contact with the layers of silicon; source/drain regions adjacent to the metal gate; a frontside power rail extending through the layers of silicon; a dielectric separating the frontside power rail from the metal gate; a via-connect buried power rail extending through the dielectric and coupling the frontside power rail to the source/drain regions; and a backside power rail coupled to the frontside power rail. The layers of silicon are wrapped on three sides by the metal gate.

Abstract: Techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. In an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. Based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. The page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. Based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. In another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.

Abstract: A method of determines one or more voltage threshold values for controlling a cooling of battery cells. The method includes determining, during e.g. charging of the battery cells, a charging voltage threshold value for starting or increasing a battery cell cooling, corresponding to a voltage across a reference set of battery cells at which a rate of change of temperature with respect to voltage of the reference set goes above a charging temperature rate threshold value. A method for using such one or more voltage threshold values for controlling a cooling of the battery cells, by comparing a measured voltage across the battery cells against the voltage threshold value(s) is also provided.

Abstract: Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.

Abstract: A method of determining ageing of a mixed electrode of a full cell lithium ion battery is presented. The method includes obtaining a voltage hysteresis of the full cell lithium ion battery by comparison of a charging voltage to a discharging voltage at a specific state of charge, SOC. The specific SOC is in a range from 0% to 20% of a maximum SOC. The method further includes determining ageing of a volume expanding component of the mixed electrode based on the obtained voltage hysteresis.

Abstract: A semiconductor structure includes a source/drain region; a frontside source/drain contact disposed on the source/drain region, a via-to-backside power rail disposed on the frontside source/drain contact and on a portion of the source/drain region, and a backside power rail connected to the via-to-backside power rail.

Abstract: A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.

Abstract: A semiconductor device includes a backside power rail; a transistor source/drain structure that has a backside facing the backside power rail and has a frontside facing away from the backside power rail; and a via disposed between and electrically connecting the backside power rail and the source/drain structure. The via includes a buried portion that is disposed between the backside power rail and the backside of the transistor source/drain structure. A part of the buried portion overlaps and contacts at least a part of the backside of the source/drain structure. The via also includes a side portion that is electrically connected with the buried portion and extends along a vertical side of the source/drain structure between the frontside and the backside; and a top portion that is electrically connected with the side portion and covers at least a part of the frontside of the source/drain structure.

Abstract: A semiconductor device includes a source/drain having a height, a length, and a width. A full wrap-around contact surrounds a partial length of the source/drain, wherein the full wrap-around contact includes a partial front-side wrap-around contact from a front side of a substrate and a partial back-side wrap-around contact from a back side of the substrate.

Abstract: A LIDAR-based method of determining an absolute speed of an object at a relatively longer distance from an ego vehicle, including: estimating a self speed of the ego vehicle using a first frame t?1 and a second frame t obtained from a LIDAR sensor by estimating an intervening rotation ? about a z axis and translation in orthogonal x and y directions using a deep learning algorithm over a relatively closer distance range; dividing each of the first frame t?1 and the second frame t into multiple adjacent input ranges and estimating a relative speed of the object at the relatively longer distance by subsequently processing each frame using a network, with each input range processed using a corresponding convolutional neural network; and combining the estimation of the estimating the self speed with the estimation of the estimating the relative speed to obtain an estimation of the absolute speed.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

Abstract: A semiconductor device includes a first transistor including a first source/drain region, and a second transistor stacked on the first transistor. The second transistor includes a second source/drain region. The semiconductor device further includes a via structure disposed between a power element and the second source/drain region. The via structure includes a first via disposed on the power element, and a second via disposed on the first via, wherein the second via is angled with respect to the first via.